source: rtems/cpukit/score/cpu/arm/rtems/score/cpu.h @ 89b85e51

4.115
Last change on this file since 89b85e51 was 89b85e51, checked in by Sebastian Huber <sebastian.huber@…>, on 07/16/10 at 08:46:29

2010-07-16 Sebastian Huber <sebastian.huber@…>

  • rtems/score/cpu.h: Include <rtems/score/types.h> first.
  • rtems/score/types.h: Use <rtems/score/basedefs.h> header file.
  • Property mode set to 100644
File size: 11.0 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup ScoreCPU
5 *
6 * @brief ARM architecture support API.
7 */
8
9/*
10 * $Id$
11 *
12 *  This include file contains information pertaining to the ARM
13 *  processor.
14 *
15 *  Copyright (c) 2009 embedded brains GmbH.
16 *
17 *  Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com>
18 *
19 *  Copyright (c) 2006 OAR Corporation
20 *
21 *  Copyright (c) 2002 Advent Networks, Inc.
22 *        Jay Monkman <jmonkman@adventnetworks.com>
23 *
24 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
25 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
26 *
27 *  The license and distribution terms for this file may be
28 *  found in the file LICENSE in this distribution or at
29 *  http://www.rtems.com/license/LICENSE.
30 *
31 */
32
33#ifndef _RTEMS_SCORE_CPU_H
34#define _RTEMS_SCORE_CPU_H
35
36#include <rtems/score/types.h>
37#include <rtems/score/arm.h>
38
39/**
40 * @defgroup ScoreCPUARM ARM Specific Support
41 *
42 * @ingroup ScoreCPU
43 *
44 * @brief ARM specific support.
45 *
46 * @{
47 */
48
49#ifdef __thumb__
50  #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg
51  #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n"
52  #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n"
53  #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg)
54  #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT
55#else
56  #define ARM_SWITCH_REGISTERS
57  #define ARM_SWITCH_TO_ARM
58  #define ARM_SWITCH_BACK
59  #define ARM_SWITCH_OUTPUT
60  #define ARM_SWITCH_ADDITIONAL_OUTPUT
61#endif
62
63/**
64 * @name Program Status Register
65 *
66 * @{
67 */
68
69#define ARM_PSR_N (1 << 31)
70#define ARM_PSR_Z (1 << 30)
71#define ARM_PSR_C (1 << 29)
72#define ARM_PSR_V (1 << 28)
73#define ARM_PSR_Q (1 << 27)
74#define ARM_PSR_J (1 << 24)
75#define ARM_PSR_GE_SHIFT 16
76#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT)
77#define ARM_PSR_E (1 << 9)
78#define ARM_PSR_A (1 << 8)
79#define ARM_PSR_I (1 << 7)
80#define ARM_PSR_F (1 << 6)
81#define ARM_PSR_T (1 << 5)
82#define ARM_PSR_M_SHIFT 0
83#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT)
84#define ARM_PSR_M_USR 0x10
85#define ARM_PSR_M_FIQ 0x11
86#define ARM_PSR_M_IRQ 0x12
87#define ARM_PSR_M_SVC 0x13
88#define ARM_PSR_M_ABT 0x17
89#define ARM_PSR_M_UND 0x1b
90#define ARM_PSR_M_SYS 0x1f
91
92/** @} */
93
94/** @} */
95
96/**
97 * @addtogroup ScoreCPU
98 *
99 * @{
100 */
101
102/* If someone uses THUMB we assume she wants minimal code size */
103#ifdef __thumb__
104  #define CPU_INLINE_ENABLE_DISPATCH FALSE
105#else
106  #define CPU_INLINE_ENABLE_DISPATCH TRUE
107#endif
108
109#if defined(__ARMEL__)
110  #define CPU_BIG_ENDIAN FALSE
111  #define CPU_LITTLE_ENDIAN TRUE
112#elif defined(__ARMEB__)
113  #define CPU_BIG_ENDIAN TRUE
114  #define CPU_LITTLE_ENDIAN FALSE
115#else
116  #error "unknown endianness"
117#endif
118
119#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
120
121#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
122
123#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
124
125#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
126
127#define CPU_ISR_PASSES_FRAME_POINTER 0
128
129#if ( ARM_HAS_FPU == 1 )
130  #define CPU_HARDWARE_FP TRUE
131#else
132  #define CPU_HARDWARE_FP FALSE
133#endif
134
135#define CPU_SOFTWARE_FP FALSE
136
137#define CPU_ALL_TASKS_ARE_FP FALSE
138
139#define CPU_IDLE_TASK_IS_FP FALSE
140
141#define CPU_USE_DEFERRED_FP_SWITCH FALSE
142
143#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
144
145#define CPU_STACK_GROWS_UP FALSE
146
147/* XXX Why 32? */
148#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32)))
149
150/*
151 * The interrupt mask disables only normal interrupts (IRQ).
152 *
153 * In order to support fast interrupts (FIQ) such that they can do something
154 * useful, we have to disable the operating system support for FIQs.  Having
155 * operating system support for them would require that FIQs are disabled
156 * during critical sections of the operating system and application.  At this
157 * level IRQs and FIQs would be equal.  It is true that FIQs could interrupt
158 * the non critical sections of IRQs, so here they would have a small
159 * advantage.  Without operating system support, the FIQs can execute at any
160 * time (of course not during the service of another FIQ). If someone needs
161 * operating system support for a FIQ, she can trigger a software interrupt and
162 * service the request in a two-step process.
163 */
164#define CPU_MODES_INTERRUPT_MASK 0x80
165
166#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
167
168#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
169
170#define CPU_INTERRUPT_NUMBER_OF_VECTORS 8
171
172#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
173
174#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
175
176#define CPU_STACK_MINIMUM_SIZE (1024 * 4)
177
178#define CPU_ALIGNMENT 4
179
180#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
181
182#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
183
184#define CPU_STACK_ALIGNMENT 4
185
186/*
187 * Bitfield handler macros.
188 *
189 * If we had a particularly fast function for finding the first
190 * bit set in a word, it would go here. Since we don't (*), we'll
191 * just use the universal macros.
192 *
193 * (*) On ARM V5 and later, there's a CLZ function which could be
194 *     used to implement much quicker than the default macro.
195 */
196
197#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
198
199#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
200
201/** @} */
202
203#ifndef ASM
204
205#ifdef __cplusplus
206extern "C" {
207#endif
208
209/**
210 * @addtogroup ScoreCPU
211 *
212 * @{
213 */
214
215typedef struct {
216  uint32_t register_cpsr;
217  uint32_t register_r4;
218  uint32_t register_r5;
219  uint32_t register_r6;
220  uint32_t register_r7;
221  uint32_t register_r8;
222  uint32_t register_r9;
223  uint32_t register_r10;
224  uint32_t register_fp;
225  uint32_t register_sp;
226  uint32_t register_lr;
227  uint32_t register_pc;
228} Context_Control;
229
230typedef struct {
231  /* Not supported */
232} Context_Control_fp;
233
234SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
235
236extern uint32_t arm_cpu_mode;
237
238static inline uint32_t arm_interrupt_disable( void )
239{
240  uint32_t arm_switch_reg;
241  uint32_t level;
242
243  asm volatile (
244    ARM_SWITCH_TO_ARM
245    "mrs %[level], cpsr\n"
246    "orr %[arm_switch_reg], %[level], #0x80\n"
247    "msr cpsr, %[arm_switch_reg]\n"
248    ARM_SWITCH_BACK
249    : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level)
250  );
251
252  return level;
253}
254
255static inline void arm_interrupt_enable( uint32_t level )
256{
257  ARM_SWITCH_REGISTERS;
258
259  asm volatile (
260    ARM_SWITCH_TO_ARM
261    "msr cpsr, %[level]\n"
262    ARM_SWITCH_BACK
263    : ARM_SWITCH_OUTPUT
264    : [level] "r" (level)
265  );
266}
267
268static inline void arm_interrupt_flash( uint32_t level )
269{
270  uint32_t arm_switch_reg;
271
272  asm volatile (
273    ARM_SWITCH_TO_ARM
274    "mrs %[arm_switch_reg], cpsr\n"
275    "msr cpsr, %[level]\n"
276    "msr cpsr, %[arm_switch_reg]\n"
277    ARM_SWITCH_BACK
278    : [arm_switch_reg] "=&r" (arm_switch_reg)
279    : [level] "r" (level)
280  );
281}
282
283#define _CPU_ISR_Disable( _isr_cookie ) \
284  do { \
285    _isr_cookie = arm_interrupt_disable(); \
286  } while (0)
287
288#define _CPU_ISR_Enable( _isr_cookie )  \
289  arm_interrupt_enable( _isr_cookie )
290
291#define _CPU_ISR_Flash( _isr_cookie ) \
292  arm_interrupt_flash( _isr_cookie )
293
294void _CPU_ISR_Set_level( uint32_t level );
295
296uint32_t _CPU_ISR_Get_level( void );
297
298void _CPU_Context_Initialize(
299  Context_Control *the_context,
300  uint32_t *stack_base,
301  uint32_t size,
302  uint32_t new_level,
303  void *entry_point,
304  bool is_fp
305);
306
307#define _CPU_Context_Get_SP( _context ) \
308  (_context)->register_sp
309
310#define _CPU_Context_Restart_self( _the_context ) \
311   _CPU_Context_restore( (_the_context) );
312
313#define _CPU_Context_Fp_start( _base, _offset ) \
314   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
315
316#define _CPU_Context_Initialize_fp( _destination ) \
317  do { \
318    *(*(_destination)) = _CPU_Null_fp_context; \
319  } while (0)
320
321#define _CPU_Fatal_halt( _err )             \
322   do {                                     \
323     uint32_t _level;                       \
324     uint32_t _error = _err;                \
325     _CPU_ISR_Disable( _level );            \
326     asm volatile ("mov r0, %0\n"           \
327                   : "=r" (_error)          \
328                   : "0" (_error)           \
329                   : "r0" );                \
330     while (1);                             \
331   } while (0);
332
333void _CPU_Initialize( void );
334
335#define _CPU_Initialize_vectors()
336
337void _CPU_ISR_install_vector(
338  uint32_t vector,
339  proc_ptr new_handler,
340  proc_ptr *old_handler
341);
342
343void _CPU_Install_interrupt_stack( void );
344
345void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
346
347void _CPU_Context_restore( Context_Control *new_context )
348       RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
349
350void _CPU_Context_save_fp( Context_Control_fp **fp_context_ptr );
351
352void _CPU_Context_restore_fp( Context_Control_fp **fp_context_ptr );
353
354static inline uint32_t CPU_swap_u32( uint32_t value )
355{
356#if defined(__thumb__)
357  uint32_t byte1, byte2, byte3, byte4, swapped;
358
359  byte4 = (value >> 24) & 0xff;
360  byte3 = (value >> 16) & 0xff;
361  byte2 = (value >> 8)  & 0xff;
362  byte1 =  value & 0xff;
363
364  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
365  return swapped;
366#else
367  uint32_t tmp = value; /* make compiler warnings go away */
368  asm volatile ("EOR %1, %0, %0, ROR #16\n"
369                "BIC %1, %1, #0xff0000\n"
370                "MOV %0, %0, ROR #8\n"
371                "EOR %0, %0, %1, LSR #8\n"
372                : "=r" (value), "=r" (tmp)
373                : "0" (value), "1" (tmp));
374  return value;
375#endif
376}
377
378static inline uint16_t CPU_swap_u16( uint16_t value )
379{
380  return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU));
381}
382
383/** @} */
384
385/**
386 * @addtogroup ScoreCPUARM
387 *
388 * @{
389 */
390
391typedef struct {
392  uint32_t r0;
393  uint32_t r1;
394  uint32_t r2;
395  uint32_t r3;
396  uint32_t r4;
397  uint32_t r5;
398  uint32_t r6;
399  uint32_t r7;
400  uint32_t r8;
401  uint32_t r9;
402  uint32_t r10;
403  uint32_t r11;
404  uint32_t r12;
405  uint32_t sp;
406  uint32_t lr;
407  uint32_t pc;
408  uint32_t cpsr;
409} arm_cpu_context;
410
411typedef void arm_exc_abort_handler( arm_cpu_context *context );
412
413typedef enum {
414  ARM_EXCEPTION_RESET = 0,
415  ARM_EXCEPTION_UNDEF = 1,
416  ARM_EXCEPTION_SWI = 2,
417  ARM_EXCEPTION_PREF_ABORT = 3,
418  ARM_EXCEPTION_DATA_ABORT = 4,
419  ARM_EXCEPTION_RESERVED = 5,
420  ARM_EXCEPTION_IRQ = 6,
421  ARM_EXCEPTION_FIQ = 7,
422  MAX_EXCEPTIONS = 8
423} Arm_symbolic_exception_name;
424
425static inline uint32_t arm_status_irq_enable( void )
426{
427  uint32_t arm_switch_reg;
428  uint32_t psr;
429
430  RTEMS_COMPILER_MEMORY_BARRIER();
431
432  asm volatile (
433    ARM_SWITCH_TO_ARM
434    "mrs %[psr], cpsr\n"
435    "bic %[arm_switch_reg], %[psr], #0x80\n"
436    "msr cpsr, %[arm_switch_reg]\n"
437    ARM_SWITCH_BACK
438    : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr)
439  );
440
441  return psr;
442}
443
444static inline void arm_status_restore( uint32_t psr )
445{
446  ARM_SWITCH_REGISTERS;
447
448  asm volatile (
449    ARM_SWITCH_TO_ARM
450    "msr cpsr, %[psr]\n"
451    ARM_SWITCH_BACK
452    : ARM_SWITCH_OUTPUT
453    : [psr] "r" (psr)
454  );
455
456  RTEMS_COMPILER_MEMORY_BARRIER();
457}
458
459void arm_exc_data_abort_set_handler( arm_exc_abort_handler handler );
460
461void arm_exc_data_abort( void );
462
463void arm_exc_prefetch_abort_set_handler( arm_exc_abort_handler handler );
464
465void arm_exc_prefetch_abort( void );
466
467void bsp_interrupt_dispatch( void );
468
469void arm_exc_interrupt( void );
470
471void arm_exc_undefined( void );
472
473/** @} */
474
475/* XXX This is out of date */
476typedef struct {
477  uint32_t register_r0;
478  uint32_t register_r1;
479  uint32_t register_r2;
480  uint32_t register_r3;
481  uint32_t register_ip;
482  uint32_t register_lr;
483} CPU_Exception_frame;
484
485typedef CPU_Exception_frame CPU_Interrupt_frame;
486
487#ifdef __cplusplus
488}
489#endif
490
491#endif /* ASM */
492
493#endif /* _RTEMS_SCORE_CPU_H */
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