source: rtems/cpukit/score/cpu/arm/rtems/score/cpu.h @ 86820eda

4.115
Last change on this file since 86820eda was 86820eda, checked in by Sebastian Huber <sebastian.huber@…>, on 04/15/11 at 08:06:16

2011-04-15 Sebastian Huber <sebastian.huber@…>

PR 1780/cpukit

  • rtems/score/cpu.h: Lower alignment requirements for CPU_PARTITION_ALIGNMENT according to AAPCS.
  • Property mode set to 100644
File size: 11.1 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup ScoreCPU
5 *
6 * @brief ARM architecture support API.
7 */
8
9/*
10 * $Id$
11 *
12 *  This include file contains information pertaining to the ARM
13 *  processor.
14 *
15 *  Copyright (c) 2009-2010 embedded brains GmbH.
16 *
17 *  Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com>
18 *
19 *  Copyright (c) 2006 OAR Corporation
20 *
21 *  Copyright (c) 2002 Advent Networks, Inc.
22 *        Jay Monkman <jmonkman@adventnetworks.com>
23 *
24 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
25 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
26 *
27 *  The license and distribution terms for this file may be
28 *  found in the file LICENSE in this distribution or at
29 *  http://www.rtems.com/license/LICENSE.
30 *
31 */
32
33#ifndef _RTEMS_SCORE_CPU_H
34#define _RTEMS_SCORE_CPU_H
35
36#include <rtems/score/types.h>
37#include <rtems/score/arm.h>
38
39/**
40 * @defgroup ScoreCPUARM ARM Specific Support
41 *
42 * @ingroup ScoreCPU
43 *
44 * @brief ARM specific support.
45 *
46 * @{
47 */
48
49#ifdef __thumb__
50  #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg
51  #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n"
52  #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n"
53  #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg)
54  #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT
55#else
56  #define ARM_SWITCH_REGISTERS
57  #define ARM_SWITCH_TO_ARM
58  #define ARM_SWITCH_BACK
59  #define ARM_SWITCH_OUTPUT
60  #define ARM_SWITCH_ADDITIONAL_OUTPUT
61#endif
62
63/**
64 * @name Program Status Register
65 *
66 * @{
67 */
68
69#define ARM_PSR_N (1 << 31)
70#define ARM_PSR_Z (1 << 30)
71#define ARM_PSR_C (1 << 29)
72#define ARM_PSR_V (1 << 28)
73#define ARM_PSR_Q (1 << 27)
74#define ARM_PSR_J (1 << 24)
75#define ARM_PSR_GE_SHIFT 16
76#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT)
77#define ARM_PSR_E (1 << 9)
78#define ARM_PSR_A (1 << 8)
79#define ARM_PSR_I (1 << 7)
80#define ARM_PSR_F (1 << 6)
81#define ARM_PSR_T (1 << 5)
82#define ARM_PSR_M_SHIFT 0
83#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT)
84#define ARM_PSR_M_USR 0x10
85#define ARM_PSR_M_FIQ 0x11
86#define ARM_PSR_M_IRQ 0x12
87#define ARM_PSR_M_SVC 0x13
88#define ARM_PSR_M_ABT 0x17
89#define ARM_PSR_M_UND 0x1b
90#define ARM_PSR_M_SYS 0x1f
91
92/** @} */
93
94/** @} */
95
96/**
97 * @addtogroup ScoreCPU
98 *
99 * @{
100 */
101
102/* If someone uses THUMB we assume she wants minimal code size */
103#ifdef __thumb__
104  #define CPU_INLINE_ENABLE_DISPATCH FALSE
105#else
106  #define CPU_INLINE_ENABLE_DISPATCH TRUE
107#endif
108
109#if defined(__ARMEL__)
110  #define CPU_BIG_ENDIAN FALSE
111  #define CPU_LITTLE_ENDIAN TRUE
112#elif defined(__ARMEB__)
113  #define CPU_BIG_ENDIAN TRUE
114  #define CPU_LITTLE_ENDIAN FALSE
115#else
116  #error "unknown endianness"
117#endif
118
119#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
120
121#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
122
123#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
124
125#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
126
127#define CPU_ISR_PASSES_FRAME_POINTER 0
128
129#if ( ARM_HAS_FPU == 1 )
130  #define CPU_HARDWARE_FP TRUE
131#else
132  #define CPU_HARDWARE_FP FALSE
133#endif
134
135#define CPU_SOFTWARE_FP FALSE
136
137#define CPU_ALL_TASKS_ARE_FP FALSE
138
139#define CPU_IDLE_TASK_IS_FP FALSE
140
141#define CPU_USE_DEFERRED_FP_SWITCH FALSE
142
143#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
144
145#define CPU_STACK_GROWS_UP FALSE
146
147/* XXX Why 32? */
148#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32)))
149
150/*
151 * The interrupt mask disables only normal interrupts (IRQ).
152 *
153 * In order to support fast interrupts (FIQ) such that they can do something
154 * useful, we have to disable the operating system support for FIQs.  Having
155 * operating system support for them would require that FIQs are disabled
156 * during critical sections of the operating system and application.  At this
157 * level IRQs and FIQs would be equal.  It is true that FIQs could interrupt
158 * the non critical sections of IRQs, so here they would have a small
159 * advantage.  Without operating system support, the FIQs can execute at any
160 * time (of course not during the service of another FIQ). If someone needs
161 * operating system support for a FIQ, she can trigger a software interrupt and
162 * service the request in a two-step process.
163 */
164#define CPU_MODES_INTERRUPT_MASK 0x80
165
166#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
167
168#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
169
170#define CPU_INTERRUPT_NUMBER_OF_VECTORS 8
171
172#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
173
174#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
175
176#define CPU_STACK_MINIMUM_SIZE (1024 * 4)
177
178/* AAPCS, section 4.1, Fundamental Data Types */
179#define CPU_ALIGNMENT 8
180
181#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
182
183/* AAPCS, section 4.3.1, Aggregates */
184#define CPU_PARTITION_ALIGNMENT 4
185
186/* AAPCS, section 5.2.1.2, Stack constraints at a public interface */
187#define CPU_STACK_ALIGNMENT 8
188
189/*
190 * Bitfield handler macros.
191 *
192 * If we had a particularly fast function for finding the first
193 * bit set in a word, it would go here. Since we don't (*), we'll
194 * just use the universal macros.
195 *
196 * (*) On ARM V5 and later, there's a CLZ function which could be
197 *     used to implement much quicker than the default macro.
198 */
199
200#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
201
202#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
203
204/** @} */
205
206#ifndef ASM
207
208#ifdef __cplusplus
209extern "C" {
210#endif
211
212/**
213 * @addtogroup ScoreCPU
214 *
215 * @{
216 */
217
218typedef struct {
219  uint32_t register_cpsr;
220  uint32_t register_r4;
221  uint32_t register_r5;
222  uint32_t register_r6;
223  uint32_t register_r7;
224  uint32_t register_r8;
225  uint32_t register_r9;
226  uint32_t register_r10;
227  uint32_t register_fp;
228  uint32_t register_sp;
229  uint32_t register_lr;
230  uint32_t register_pc;
231} Context_Control;
232
233typedef struct {
234  /* Not supported */
235} Context_Control_fp;
236
237SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
238
239extern uint32_t arm_cpu_mode;
240
241static inline uint32_t arm_interrupt_disable( void )
242{
243  uint32_t arm_switch_reg;
244  uint32_t level;
245
246  __asm__ volatile (
247    ARM_SWITCH_TO_ARM
248    "mrs %[level], cpsr\n"
249    "orr %[arm_switch_reg], %[level], #0x80\n"
250    "msr cpsr, %[arm_switch_reg]\n"
251    ARM_SWITCH_BACK
252    : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level)
253  );
254
255  return level;
256}
257
258static inline void arm_interrupt_enable( uint32_t level )
259{
260  ARM_SWITCH_REGISTERS;
261
262  __asm__ volatile (
263    ARM_SWITCH_TO_ARM
264    "msr cpsr, %[level]\n"
265    ARM_SWITCH_BACK
266    : ARM_SWITCH_OUTPUT
267    : [level] "r" (level)
268  );
269}
270
271static inline void arm_interrupt_flash( uint32_t level )
272{
273  uint32_t arm_switch_reg;
274
275  __asm__ volatile (
276    ARM_SWITCH_TO_ARM
277    "mrs %[arm_switch_reg], cpsr\n"
278    "msr cpsr, %[level]\n"
279    "msr cpsr, %[arm_switch_reg]\n"
280    ARM_SWITCH_BACK
281    : [arm_switch_reg] "=&r" (arm_switch_reg)
282    : [level] "r" (level)
283  );
284}
285
286#define _CPU_ISR_Disable( _isr_cookie ) \
287  do { \
288    _isr_cookie = arm_interrupt_disable(); \
289  } while (0)
290
291#define _CPU_ISR_Enable( _isr_cookie )  \
292  arm_interrupt_enable( _isr_cookie )
293
294#define _CPU_ISR_Flash( _isr_cookie ) \
295  arm_interrupt_flash( _isr_cookie )
296
297void _CPU_ISR_Set_level( uint32_t level );
298
299uint32_t _CPU_ISR_Get_level( void );
300
301void _CPU_Context_Initialize(
302  Context_Control *the_context,
303  uint32_t *stack_base,
304  uint32_t size,
305  uint32_t new_level,
306  void *entry_point,
307  bool is_fp
308);
309
310#define _CPU_Context_Get_SP( _context ) \
311  (_context)->register_sp
312
313#define _CPU_Context_Restart_self( _the_context ) \
314   _CPU_Context_restore( (_the_context) );
315
316#define _CPU_Context_Fp_start( _base, _offset ) \
317   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
318
319#define _CPU_Context_Initialize_fp( _destination ) \
320  do { \
321    *(*(_destination)) = _CPU_Null_fp_context; \
322  } while (0)
323
324#define _CPU_Fatal_halt( _err )             \
325   do {                                     \
326     uint32_t _level;                       \
327     uint32_t _error = _err;                \
328     _CPU_ISR_Disable( _level );            \
329     __asm__ volatile ("mov r0, %0\n"           \
330                   : "=r" (_error)          \
331                   : "0" (_error)           \
332                   : "r0" );                \
333     while (1);                             \
334   } while (0);
335
336void _CPU_Initialize( void );
337
338#define _CPU_Initialize_vectors()
339
340void _CPU_ISR_install_vector(
341  uint32_t vector,
342  proc_ptr new_handler,
343  proc_ptr *old_handler
344);
345
346void _CPU_Install_interrupt_stack( void );
347
348void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
349
350void _CPU_Context_restore( Context_Control *new_context )
351       RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
352
353void _CPU_Context_save_fp( Context_Control_fp **fp_context_ptr );
354
355void _CPU_Context_restore_fp( Context_Control_fp **fp_context_ptr );
356
357static inline uint32_t CPU_swap_u32( uint32_t value )
358{
359#if defined(__thumb__)
360  uint32_t byte1, byte2, byte3, byte4, swapped;
361
362  byte4 = (value >> 24) & 0xff;
363  byte3 = (value >> 16) & 0xff;
364  byte2 = (value >> 8)  & 0xff;
365  byte1 =  value & 0xff;
366
367  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
368  return swapped;
369#else
370  uint32_t tmp = value; /* make compiler warnings go away */
371  __asm__ volatile ("EOR %1, %0, %0, ROR #16\n"
372                "BIC %1, %1, #0xff0000\n"
373                "MOV %0, %0, ROR #8\n"
374                "EOR %0, %0, %1, LSR #8\n"
375                : "=r" (value), "=r" (tmp)
376                : "0" (value), "1" (tmp));
377  return value;
378#endif
379}
380
381static inline uint16_t CPU_swap_u16( uint16_t value )
382{
383  return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU));
384}
385
386/** @} */
387
388/**
389 * @addtogroup ScoreCPUARM
390 *
391 * @{
392 */
393
394typedef struct {
395  uint32_t r0;
396  uint32_t r1;
397  uint32_t r2;
398  uint32_t r3;
399  uint32_t r4;
400  uint32_t r5;
401  uint32_t r6;
402  uint32_t r7;
403  uint32_t r8;
404  uint32_t r9;
405  uint32_t r10;
406  uint32_t r11;
407  uint32_t r12;
408  uint32_t sp;
409  uint32_t lr;
410  uint32_t pc;
411  uint32_t cpsr;
412} arm_cpu_context;
413
414typedef void arm_exc_abort_handler( arm_cpu_context *context );
415
416typedef enum {
417  ARM_EXCEPTION_RESET = 0,
418  ARM_EXCEPTION_UNDEF = 1,
419  ARM_EXCEPTION_SWI = 2,
420  ARM_EXCEPTION_PREF_ABORT = 3,
421  ARM_EXCEPTION_DATA_ABORT = 4,
422  ARM_EXCEPTION_RESERVED = 5,
423  ARM_EXCEPTION_IRQ = 6,
424  ARM_EXCEPTION_FIQ = 7,
425  MAX_EXCEPTIONS = 8
426} Arm_symbolic_exception_name;
427
428static inline uint32_t arm_status_irq_enable( void )
429{
430  uint32_t arm_switch_reg;
431  uint32_t psr;
432
433  RTEMS_COMPILER_MEMORY_BARRIER();
434
435  __asm__ volatile (
436    ARM_SWITCH_TO_ARM
437    "mrs %[psr], cpsr\n"
438    "bic %[arm_switch_reg], %[psr], #0x80\n"
439    "msr cpsr, %[arm_switch_reg]\n"
440    ARM_SWITCH_BACK
441    : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr)
442  );
443
444  return psr;
445}
446
447static inline void arm_status_restore( uint32_t psr )
448{
449  ARM_SWITCH_REGISTERS;
450
451  __asm__ volatile (
452    ARM_SWITCH_TO_ARM
453    "msr cpsr, %[psr]\n"
454    ARM_SWITCH_BACK
455    : ARM_SWITCH_OUTPUT
456    : [psr] "r" (psr)
457  );
458
459  RTEMS_COMPILER_MEMORY_BARRIER();
460}
461
462void arm_exc_data_abort_set_handler( arm_exc_abort_handler handler );
463
464void arm_exc_data_abort( void );
465
466void arm_exc_prefetch_abort_set_handler( arm_exc_abort_handler handler );
467
468void arm_exc_prefetch_abort( void );
469
470void bsp_interrupt_dispatch( void );
471
472void arm_exc_interrupt( void );
473
474void arm_exc_undefined( void );
475
476/** @} */
477
478/* XXX This is out of date */
479typedef struct {
480  uint32_t register_r0;
481  uint32_t register_r1;
482  uint32_t register_r2;
483  uint32_t register_r3;
484  uint32_t register_ip;
485  uint32_t register_lr;
486} CPU_Exception_frame;
487
488typedef CPU_Exception_frame CPU_Interrupt_frame;
489
490#ifdef __cplusplus
491}
492#endif
493
494#endif /* ASM */
495
496#endif /* _RTEMS_SCORE_CPU_H */
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