1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup ScoreCPU |
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5 | * |
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6 | * @brief ARM architecture support API. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * $Id$ |
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11 | * |
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12 | * This include file contains information pertaining to the ARM |
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13 | * processor. |
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14 | * |
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15 | * Copyright (c) 2009-2010 embedded brains GmbH. |
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16 | * |
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17 | * Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com> |
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18 | * |
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19 | * Copyright (c) 2006 OAR Corporation |
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20 | * |
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21 | * Copyright (c) 2002 Advent Networks, Inc. |
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22 | * Jay Monkman <jmonkman@adventnetworks.com> |
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23 | * |
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24 | * COPYRIGHT (c) 2000 Canon Research Centre France SA. |
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25 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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26 | * |
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27 | * The license and distribution terms for this file may be |
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28 | * found in the file LICENSE in this distribution or at |
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29 | * http://www.rtems.com/license/LICENSE. |
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30 | * |
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31 | */ |
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32 | |
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33 | #ifndef _RTEMS_SCORE_CPU_H |
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34 | #define _RTEMS_SCORE_CPU_H |
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35 | |
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36 | #include <rtems/score/types.h> |
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37 | #include <rtems/score/arm.h> |
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38 | |
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39 | /** |
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40 | * @defgroup ScoreCPUARM ARM Specific Support |
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41 | * |
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42 | * @ingroup ScoreCPU |
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43 | * |
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44 | * @brief ARM specific support. |
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45 | * |
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46 | * @{ |
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47 | */ |
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48 | |
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49 | #ifdef __thumb__ |
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50 | #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg |
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51 | #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n" |
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52 | #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n" |
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53 | #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg) |
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54 | #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT |
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55 | #else |
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56 | #define ARM_SWITCH_REGISTERS |
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57 | #define ARM_SWITCH_TO_ARM |
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58 | #define ARM_SWITCH_BACK |
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59 | #define ARM_SWITCH_OUTPUT |
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60 | #define ARM_SWITCH_ADDITIONAL_OUTPUT |
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61 | #endif |
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62 | |
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63 | /** |
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64 | * @name Program Status Register |
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65 | * |
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66 | * @{ |
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67 | */ |
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68 | |
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69 | #define ARM_PSR_N (1 << 31) |
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70 | #define ARM_PSR_Z (1 << 30) |
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71 | #define ARM_PSR_C (1 << 29) |
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72 | #define ARM_PSR_V (1 << 28) |
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73 | #define ARM_PSR_Q (1 << 27) |
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74 | #define ARM_PSR_J (1 << 24) |
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75 | #define ARM_PSR_GE_SHIFT 16 |
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76 | #define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT) |
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77 | #define ARM_PSR_E (1 << 9) |
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78 | #define ARM_PSR_A (1 << 8) |
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79 | #define ARM_PSR_I (1 << 7) |
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80 | #define ARM_PSR_F (1 << 6) |
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81 | #define ARM_PSR_T (1 << 5) |
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82 | #define ARM_PSR_M_SHIFT 0 |
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83 | #define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT) |
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84 | #define ARM_PSR_M_USR 0x10 |
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85 | #define ARM_PSR_M_FIQ 0x11 |
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86 | #define ARM_PSR_M_IRQ 0x12 |
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87 | #define ARM_PSR_M_SVC 0x13 |
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88 | #define ARM_PSR_M_ABT 0x17 |
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89 | #define ARM_PSR_M_UND 0x1b |
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90 | #define ARM_PSR_M_SYS 0x1f |
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91 | |
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92 | /** @} */ |
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93 | |
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94 | /** @} */ |
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95 | |
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96 | /** |
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97 | * @addtogroup ScoreCPU |
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98 | * |
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99 | * @{ |
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100 | */ |
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101 | |
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102 | /* If someone uses THUMB we assume she wants minimal code size */ |
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103 | #ifdef __thumb__ |
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104 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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105 | #else |
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106 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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107 | #endif |
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108 | |
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109 | #if defined(__ARMEL__) |
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110 | #define CPU_BIG_ENDIAN FALSE |
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111 | #define CPU_LITTLE_ENDIAN TRUE |
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112 | #elif defined(__ARMEB__) |
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113 | #define CPU_BIG_ENDIAN TRUE |
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114 | #define CPU_LITTLE_ENDIAN FALSE |
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115 | #else |
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116 | #error "unknown endianness" |
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117 | #endif |
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118 | |
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119 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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120 | |
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121 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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122 | |
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123 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
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124 | |
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125 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
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126 | |
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127 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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128 | |
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129 | #if ( ARM_HAS_FPU == 1 ) |
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130 | #define CPU_HARDWARE_FP TRUE |
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131 | #else |
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132 | #define CPU_HARDWARE_FP FALSE |
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133 | #endif |
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134 | |
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135 | #define CPU_SOFTWARE_FP FALSE |
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136 | |
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137 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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138 | |
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139 | #define CPU_IDLE_TASK_IS_FP FALSE |
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140 | |
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141 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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142 | |
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143 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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144 | |
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145 | #define CPU_STACK_GROWS_UP FALSE |
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146 | |
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147 | /* XXX Why 32? */ |
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148 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) |
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149 | |
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150 | /* |
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151 | * The interrupt mask disables only normal interrupts (IRQ). |
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152 | * |
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153 | * In order to support fast interrupts (FIQ) such that they can do something |
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154 | * useful, we have to disable the operating system support for FIQs. Having |
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155 | * operating system support for them would require that FIQs are disabled |
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156 | * during critical sections of the operating system and application. At this |
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157 | * level IRQs and FIQs would be equal. It is true that FIQs could interrupt |
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158 | * the non critical sections of IRQs, so here they would have a small |
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159 | * advantage. Without operating system support, the FIQs can execute at any |
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160 | * time (of course not during the service of another FIQ). If someone needs |
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161 | * operating system support for a FIQ, she can trigger a software interrupt and |
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162 | * service the request in a two-step process. |
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163 | */ |
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164 | #define CPU_MODES_INTERRUPT_MASK 0x80 |
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165 | |
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166 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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167 | |
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168 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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169 | |
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170 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 8 |
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171 | |
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172 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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173 | |
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174 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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175 | |
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176 | #define CPU_STACK_MINIMUM_SIZE (1024 * 4) |
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177 | |
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178 | /* AAPCS, section 4.1, Fundamental Data Types */ |
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179 | #define CPU_ALIGNMENT 8 |
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180 | |
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181 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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182 | |
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183 | /* AAPCS, section 4.3.1, Aggregates */ |
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184 | #define CPU_PARTITION_ALIGNMENT 4 |
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185 | |
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186 | /* AAPCS, section 5.2.1.2, Stack constraints at a public interface */ |
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187 | #define CPU_STACK_ALIGNMENT 8 |
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188 | |
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189 | /* |
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190 | * Bitfield handler macros. |
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191 | * |
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192 | * If we had a particularly fast function for finding the first |
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193 | * bit set in a word, it would go here. Since we don't (*), we'll |
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194 | * just use the universal macros. |
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195 | * |
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196 | * (*) On ARM V5 and later, there's a CLZ function which could be |
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197 | * used to implement much quicker than the default macro. |
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198 | */ |
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199 | |
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200 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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201 | |
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202 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
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203 | |
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204 | /** @} */ |
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205 | |
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206 | #ifndef ASM |
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207 | |
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208 | #ifdef __cplusplus |
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209 | extern "C" { |
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210 | #endif |
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211 | |
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212 | /** |
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213 | * @addtogroup ScoreCPU |
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214 | * |
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215 | * @{ |
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216 | */ |
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217 | |
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218 | typedef struct { |
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219 | uint32_t register_cpsr; |
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220 | uint32_t register_r4; |
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221 | uint32_t register_r5; |
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222 | uint32_t register_r6; |
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223 | uint32_t register_r7; |
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224 | uint32_t register_r8; |
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225 | uint32_t register_r9; |
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226 | uint32_t register_r10; |
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227 | uint32_t register_fp; |
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228 | uint32_t register_sp; |
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229 | uint32_t register_lr; |
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230 | uint32_t register_pc; |
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231 | } Context_Control; |
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232 | |
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233 | typedef struct { |
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234 | /* Not supported */ |
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235 | } Context_Control_fp; |
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236 | |
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237 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
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238 | |
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239 | extern uint32_t arm_cpu_mode; |
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240 | |
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241 | static inline uint32_t arm_interrupt_disable( void ) |
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242 | { |
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243 | uint32_t arm_switch_reg; |
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244 | uint32_t level; |
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245 | |
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246 | __asm__ volatile ( |
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247 | ARM_SWITCH_TO_ARM |
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248 | "mrs %[level], cpsr\n" |
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249 | "orr %[arm_switch_reg], %[level], #0x80\n" |
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250 | "msr cpsr, %[arm_switch_reg]\n" |
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251 | ARM_SWITCH_BACK |
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252 | : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level) |
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253 | ); |
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254 | |
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255 | return level; |
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256 | } |
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257 | |
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258 | static inline void arm_interrupt_enable( uint32_t level ) |
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259 | { |
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260 | ARM_SWITCH_REGISTERS; |
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261 | |
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262 | __asm__ volatile ( |
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263 | ARM_SWITCH_TO_ARM |
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264 | "msr cpsr, %[level]\n" |
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265 | ARM_SWITCH_BACK |
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266 | : ARM_SWITCH_OUTPUT |
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267 | : [level] "r" (level) |
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268 | ); |
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269 | } |
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270 | |
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271 | static inline void arm_interrupt_flash( uint32_t level ) |
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272 | { |
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273 | uint32_t arm_switch_reg; |
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274 | |
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275 | __asm__ volatile ( |
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276 | ARM_SWITCH_TO_ARM |
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277 | "mrs %[arm_switch_reg], cpsr\n" |
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278 | "msr cpsr, %[level]\n" |
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279 | "msr cpsr, %[arm_switch_reg]\n" |
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280 | ARM_SWITCH_BACK |
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281 | : [arm_switch_reg] "=&r" (arm_switch_reg) |
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282 | : [level] "r" (level) |
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283 | ); |
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284 | } |
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285 | |
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286 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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287 | do { \ |
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288 | _isr_cookie = arm_interrupt_disable(); \ |
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289 | } while (0) |
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290 | |
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291 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
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292 | arm_interrupt_enable( _isr_cookie ) |
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293 | |
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294 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
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295 | arm_interrupt_flash( _isr_cookie ) |
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296 | |
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297 | void _CPU_ISR_Set_level( uint32_t level ); |
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298 | |
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299 | uint32_t _CPU_ISR_Get_level( void ); |
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300 | |
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301 | void _CPU_Context_Initialize( |
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302 | Context_Control *the_context, |
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303 | uint32_t *stack_base, |
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304 | uint32_t size, |
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305 | uint32_t new_level, |
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306 | void *entry_point, |
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307 | bool is_fp |
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308 | ); |
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309 | |
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310 | #define _CPU_Context_Get_SP( _context ) \ |
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311 | (_context)->register_sp |
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312 | |
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313 | #define _CPU_Context_Restart_self( _the_context ) \ |
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314 | _CPU_Context_restore( (_the_context) ); |
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315 | |
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316 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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317 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
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318 | |
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319 | #define _CPU_Context_Initialize_fp( _destination ) \ |
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320 | do { \ |
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321 | *(*(_destination)) = _CPU_Null_fp_context; \ |
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322 | } while (0) |
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323 | |
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324 | #define _CPU_Fatal_halt( _err ) \ |
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325 | do { \ |
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326 | uint32_t _level; \ |
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327 | uint32_t _error = _err; \ |
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328 | _CPU_ISR_Disable( _level ); \ |
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329 | __asm__ volatile ("mov r0, %0\n" \ |
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330 | : "=r" (_error) \ |
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331 | : "0" (_error) \ |
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332 | : "r0" ); \ |
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333 | while (1); \ |
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334 | } while (0); |
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335 | |
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336 | void _CPU_Initialize( void ); |
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337 | |
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338 | #define _CPU_Initialize_vectors() |
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339 | |
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340 | void _CPU_ISR_install_vector( |
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341 | uint32_t vector, |
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342 | proc_ptr new_handler, |
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343 | proc_ptr *old_handler |
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344 | ); |
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345 | |
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346 | void _CPU_Install_interrupt_stack( void ); |
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347 | |
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348 | void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); |
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349 | |
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350 | void _CPU_Context_restore( Context_Control *new_context ) |
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351 | RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
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352 | |
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353 | void _CPU_Context_save_fp( Context_Control_fp **fp_context_ptr ); |
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354 | |
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355 | void _CPU_Context_restore_fp( Context_Control_fp **fp_context_ptr ); |
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356 | |
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357 | static inline uint32_t CPU_swap_u32( uint32_t value ) |
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358 | { |
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359 | #if defined(__thumb__) |
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360 | uint32_t byte1, byte2, byte3, byte4, swapped; |
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361 | |
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362 | byte4 = (value >> 24) & 0xff; |
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363 | byte3 = (value >> 16) & 0xff; |
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364 | byte2 = (value >> 8) & 0xff; |
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365 | byte1 = value & 0xff; |
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366 | |
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367 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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368 | return swapped; |
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369 | #else |
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370 | uint32_t tmp = value; /* make compiler warnings go away */ |
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371 | __asm__ volatile ("EOR %1, %0, %0, ROR #16\n" |
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372 | "BIC %1, %1, #0xff0000\n" |
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373 | "MOV %0, %0, ROR #8\n" |
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374 | "EOR %0, %0, %1, LSR #8\n" |
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375 | : "=r" (value), "=r" (tmp) |
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376 | : "0" (value), "1" (tmp)); |
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377 | return value; |
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378 | #endif |
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379 | } |
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380 | |
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381 | static inline uint16_t CPU_swap_u16( uint16_t value ) |
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382 | { |
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383 | return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU)); |
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384 | } |
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385 | |
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386 | /** @} */ |
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387 | |
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388 | /** |
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389 | * @addtogroup ScoreCPUARM |
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390 | * |
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391 | * @{ |
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392 | */ |
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393 | |
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394 | typedef struct { |
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395 | uint32_t r0; |
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396 | uint32_t r1; |
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397 | uint32_t r2; |
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398 | uint32_t r3; |
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399 | uint32_t r4; |
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400 | uint32_t r5; |
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401 | uint32_t r6; |
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402 | uint32_t r7; |
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403 | uint32_t r8; |
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404 | uint32_t r9; |
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405 | uint32_t r10; |
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406 | uint32_t r11; |
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407 | uint32_t r12; |
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408 | uint32_t sp; |
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409 | uint32_t lr; |
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410 | uint32_t pc; |
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411 | uint32_t cpsr; |
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412 | } arm_cpu_context; |
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413 | |
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414 | typedef void arm_exc_abort_handler( arm_cpu_context *context ); |
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415 | |
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416 | typedef enum { |
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417 | ARM_EXCEPTION_RESET = 0, |
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418 | ARM_EXCEPTION_UNDEF = 1, |
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419 | ARM_EXCEPTION_SWI = 2, |
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420 | ARM_EXCEPTION_PREF_ABORT = 3, |
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421 | ARM_EXCEPTION_DATA_ABORT = 4, |
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422 | ARM_EXCEPTION_RESERVED = 5, |
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423 | ARM_EXCEPTION_IRQ = 6, |
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424 | ARM_EXCEPTION_FIQ = 7, |
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425 | MAX_EXCEPTIONS = 8 |
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426 | } Arm_symbolic_exception_name; |
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427 | |
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428 | static inline uint32_t arm_status_irq_enable( void ) |
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429 | { |
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430 | uint32_t arm_switch_reg; |
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431 | uint32_t psr; |
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432 | |
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433 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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434 | |
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435 | __asm__ volatile ( |
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436 | ARM_SWITCH_TO_ARM |
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437 | "mrs %[psr], cpsr\n" |
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438 | "bic %[arm_switch_reg], %[psr], #0x80\n" |
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439 | "msr cpsr, %[arm_switch_reg]\n" |
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440 | ARM_SWITCH_BACK |
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441 | : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr) |
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442 | ); |
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443 | |
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444 | return psr; |
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445 | } |
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446 | |
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447 | static inline void arm_status_restore( uint32_t psr ) |
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448 | { |
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449 | ARM_SWITCH_REGISTERS; |
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450 | |
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451 | __asm__ volatile ( |
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452 | ARM_SWITCH_TO_ARM |
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453 | "msr cpsr, %[psr]\n" |
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454 | ARM_SWITCH_BACK |
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455 | : ARM_SWITCH_OUTPUT |
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456 | : [psr] "r" (psr) |
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457 | ); |
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458 | |
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459 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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460 | } |
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461 | |
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462 | void arm_exc_data_abort_set_handler( arm_exc_abort_handler handler ); |
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463 | |
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464 | void arm_exc_data_abort( void ); |
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465 | |
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466 | void arm_exc_prefetch_abort_set_handler( arm_exc_abort_handler handler ); |
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467 | |
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468 | void arm_exc_prefetch_abort( void ); |
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469 | |
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470 | void bsp_interrupt_dispatch( void ); |
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471 | |
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472 | void arm_exc_interrupt( void ); |
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473 | |
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474 | void arm_exc_undefined( void ); |
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475 | |
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476 | /** @} */ |
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477 | |
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478 | /* XXX This is out of date */ |
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479 | typedef struct { |
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480 | uint32_t register_r0; |
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481 | uint32_t register_r1; |
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482 | uint32_t register_r2; |
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483 | uint32_t register_r3; |
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484 | uint32_t register_ip; |
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485 | uint32_t register_lr; |
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486 | } CPU_Exception_frame; |
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487 | |
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488 | typedef CPU_Exception_frame CPU_Interrupt_frame; |
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489 | |
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490 | #ifdef __cplusplus |
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491 | } |
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492 | #endif |
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493 | |
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494 | #endif /* ASM */ |
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495 | |
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496 | #endif /* _RTEMS_SCORE_CPU_H */ |
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