source: rtems/cpukit/score/cpu/arm/rtems/score/cpu.h @ 78623bce

4.104.11
Last change on this file since 78623bce was 78623bce, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Apr 8, 2010 at 10:13:46 AM

add/adapt documentation

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1/**
2 * @file
3 *
4 * @ingroup ScoreCPU
5 *
6 * @brief ARM architecture support API.
7 */
8
9/*
10 * $Id$
11 *
12 *  This include file contains information pertaining to the ARM
13 *  processor.
14 *
15 *  Copyright (c) 2009 embedded brains GmbH.
16 *
17 *  Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com>
18 *
19 *  Copyright (c) 2006 OAR Corporation
20 *
21 *  Copyright (c) 2002 Advent Networks, Inc.
22 *        Jay Monkman <jmonkman@adventnetworks.com>
23 *
24 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
25 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
26 *
27 *  The license and distribution terms for this file may be
28 *  found in the file LICENSE in this distribution or at
29 *  http://www.rtems.com/license/LICENSE.
30 *
31 */
32
33#ifndef _RTEMS_SCORE_CPU_H
34#define _RTEMS_SCORE_CPU_H
35
36#include <rtems/score/arm.h>
37
38#ifndef ASM
39  #include <rtems/score/types.h>
40#endif
41
42#ifndef TRUE
43  #warning "TRUE not defined"
44  #define TRUE 1
45#endif
46
47#ifndef FALSE
48  #warning "FALSE not defined"
49  #define FALSE 0
50#endif
51
52/**
53 * @defgroup ScoreCPUARM ARM Specific Support
54 *
55 * @ingroup ScoreCPU
56 *
57 * @brief ARM specific support.
58 *
59 * @{
60 */
61
62#ifdef __thumb__
63  #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg
64  #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n"
65  #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n"
66  #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg)
67  #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT
68#else
69  #define ARM_SWITCH_REGISTERS
70  #define ARM_SWITCH_TO_ARM
71  #define ARM_SWITCH_BACK
72  #define ARM_SWITCH_OUTPUT
73  #define ARM_SWITCH_ADDITIONAL_OUTPUT
74#endif
75
76/**
77 * @name Program Status Register
78 *
79 * @{
80 */
81
82#define ARM_PSR_N (1 << 31)
83#define ARM_PSR_Z (1 << 30)
84#define ARM_PSR_C (1 << 29)
85#define ARM_PSR_V (1 << 28)
86#define ARM_PSR_Q (1 << 27)
87#define ARM_PSR_J (1 << 24)
88#define ARM_PSR_GE_SHIFT 16
89#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT)
90#define ARM_PSR_E (1 << 9)
91#define ARM_PSR_A (1 << 8)
92#define ARM_PSR_I (1 << 7)
93#define ARM_PSR_F (1 << 6)
94#define ARM_PSR_T (1 << 5)
95#define ARM_PSR_M_SHIFT 0
96#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT)
97#define ARM_PSR_M_USR 0x10
98#define ARM_PSR_M_FIQ 0x11
99#define ARM_PSR_M_IRQ 0x12
100#define ARM_PSR_M_SVC 0x13
101#define ARM_PSR_M_ABT 0x17
102#define ARM_PSR_M_UND 0x1b
103#define ARM_PSR_M_SYS 0x1f
104
105/** @} */
106
107/** @} */
108
109/**
110 * @addtogroup ScoreCPU
111 *
112 * @{
113 */
114
115/* If someone uses THUMB we assume she wants minimal code size */
116#ifdef __thumb__
117  #define CPU_INLINE_ENABLE_DISPATCH FALSE
118#else
119  #define CPU_INLINE_ENABLE_DISPATCH TRUE
120#endif
121
122#if defined(__ARMEL__)
123  #define CPU_BIG_ENDIAN FALSE
124  #define CPU_LITTLE_ENDIAN TRUE
125#elif defined(__ARMEB__)
126  #define CPU_BIG_ENDIAN TRUE
127  #define CPU_LITTLE_ENDIAN FALSE
128#else
129  #error "unknown endianness"
130#endif
131
132#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
133
134#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
135
136#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
137
138#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
139
140#define CPU_ISR_PASSES_FRAME_POINTER 0
141
142#if ( ARM_HAS_FPU == 1 )
143  #define CPU_HARDWARE_FP TRUE
144#else
145  #define CPU_HARDWARE_FP FALSE
146#endif
147
148#define CPU_SOFTWARE_FP FALSE
149
150#define CPU_ALL_TASKS_ARE_FP FALSE
151
152#define CPU_IDLE_TASK_IS_FP FALSE
153
154#define CPU_USE_DEFERRED_FP_SWITCH FALSE
155
156#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
157
158#define CPU_STACK_GROWS_UP FALSE
159
160/* XXX Why 32? */
161#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32)))
162
163/*
164 * The interrupt mask disables only normal interrupts (IRQ).
165 *
166 * In order to support fast interrupts (FIQ) such that they can do something
167 * useful, we have to disable the operating system support for FIQs.  Having
168 * operating system support for them would require that FIQs are disabled
169 * during critical sections of the operating system and application.  At this
170 * level IRQs and FIQs would be equal.  It is true that FIQs could interrupt
171 * the non critical sections of IRQs, so here they would have a small
172 * advantage.  Without operating system support, the FIQs can execute at any
173 * time (of course not during the service of another FIQ). If someone needs
174 * operating system support for a FIQ, she can trigger a software interrupt and
175 * service the request in a two-step process.
176 */
177#define CPU_MODES_INTERRUPT_MASK 0x80
178
179#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
180
181#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
182
183#define CPU_INTERRUPT_NUMBER_OF_VECTORS 8
184
185#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
186
187#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
188
189#define CPU_STACK_MINIMUM_SIZE (1024 * 4)
190
191#define CPU_ALIGNMENT 4
192
193#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
194
195#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
196
197#define CPU_STACK_ALIGNMENT 4
198
199/*
200 * Bitfield handler macros.
201 *
202 * If we had a particularly fast function for finding the first
203 * bit set in a word, it would go here. Since we don't (*), we'll
204 * just use the universal macros.
205 *
206 * (*) On ARM V5 and later, there's a CLZ function which could be
207 *     used to implement much quicker than the default macro.
208 */
209
210#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
211
212#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
213
214#define CPU_ENABLE_C_ISR_DISPATCH_IMPLEMENTATION TRUE
215
216/** @} */
217
218#ifndef ASM
219
220#ifdef __cplusplus
221extern "C" {
222#endif
223
224/**
225 * @addtogroup ScoreCPU
226 *
227 * @{
228 */
229
230typedef struct {
231  uint32_t register_cpsr;
232  uint32_t register_r4;
233  uint32_t register_r5;
234  uint32_t register_r6;
235  uint32_t register_r7;
236  uint32_t register_r8;
237  uint32_t register_r9;
238  uint32_t register_r10;
239  uint32_t register_fp;
240  uint32_t register_sp;
241  uint32_t register_lr;
242  uint32_t register_pc;
243} Context_Control;
244
245typedef struct {
246  /* Not supported */
247} Context_Control_fp;
248
249SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
250
251extern uint32_t arm_cpu_mode;
252
253static inline uint32_t arm_interrupt_disable( void )
254{
255  uint32_t arm_switch_reg;
256  uint32_t level;
257
258  asm volatile (
259    ARM_SWITCH_TO_ARM
260    "mrs %[level], cpsr\n"
261    "orr %[arm_switch_reg], %[level], #0x80\n"
262    "msr cpsr, %[arm_switch_reg]\n"
263    ARM_SWITCH_BACK
264    : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level)
265  );
266
267  return level;
268}
269
270static inline void arm_interrupt_enable( uint32_t level )
271{
272  ARM_SWITCH_REGISTERS;
273
274  asm volatile (
275    ARM_SWITCH_TO_ARM
276    "msr cpsr, %[level]\n"
277    ARM_SWITCH_BACK
278    : ARM_SWITCH_OUTPUT
279    : [level] "r" (level)
280  );
281}
282
283static inline void arm_interrupt_flash( uint32_t level )
284{
285  uint32_t arm_switch_reg;
286
287  asm volatile (
288    ARM_SWITCH_TO_ARM
289    "mrs %[arm_switch_reg], cpsr\n"
290    "msr cpsr, %[level]\n"
291    "msr cpsr, %[arm_switch_reg]\n"
292    ARM_SWITCH_BACK
293    : [arm_switch_reg] "=&r" (arm_switch_reg)
294    : [level] "r" (level)
295  );
296}
297
298#define _CPU_ISR_Disable( _isr_cookie ) \
299  do { \
300    _isr_cookie = arm_interrupt_disable(); \
301  } while (0)
302
303#define _CPU_ISR_Enable( _isr_cookie )  \
304  arm_interrupt_enable( _isr_cookie )
305
306#define _CPU_ISR_Flash( _isr_cookie ) \
307  arm_interrupt_flash( _isr_cookie )
308
309void _CPU_ISR_Set_level( uint32_t level );
310
311uint32_t _CPU_ISR_Get_level( void );
312
313void _CPU_Context_Initialize(
314  Context_Control *the_context,
315  uint32_t *stack_base,
316  uint32_t size,
317  uint32_t new_level,
318  void *entry_point,
319  bool is_fp
320);
321
322#define _CPU_Context_Get_SP( _context ) \
323  (_context)->register_sp
324
325#define _CPU_Context_Restart_self( _the_context ) \
326   _CPU_Context_restore( (_the_context) );
327
328#define _CPU_Context_Fp_start( _base, _offset ) \
329   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
330
331#define _CPU_Context_Initialize_fp( _destination ) \
332  do { \
333    *(*(_destination)) = _CPU_Null_fp_context; \
334  } while (0)
335
336#define _CPU_Fatal_halt( _err )             \
337   do {                                     \
338     uint32_t _level;                       \
339     uint32_t _error = _err;                \
340     _CPU_ISR_Disable( _level );            \
341     asm volatile ("mov r0, %0\n"           \
342                   : "=r" (_error)          \
343                   : "0" (_error)           \
344                   : "r0" );                \
345     while (1);                             \
346   } while (0);
347
348void _CPU_Initialize( void );
349
350#define _CPU_Initialize_vectors()
351
352void _CPU_ISR_install_vector(
353  uint32_t vector,
354  proc_ptr new_handler,
355  proc_ptr *old_handler
356);
357
358void _CPU_Install_interrupt_stack( void );
359
360void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
361
362void _CPU_Context_restore( Context_Control *new_context )
363       RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
364
365void _CPU_Context_save_fp( Context_Control_fp **fp_context_ptr );
366
367void _CPU_Context_restore_fp( Context_Control_fp **fp_context_ptr );
368
369static inline uint32_t CPU_swap_u32( uint32_t value )
370{
371#if defined(__thumb__)
372  uint32_t byte1, byte2, byte3, byte4, swapped;
373
374  byte4 = (value >> 24) & 0xff;
375  byte3 = (value >> 16) & 0xff;
376  byte2 = (value >> 8)  & 0xff;
377  byte1 =  value & 0xff;
378
379  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
380  return swapped;
381#else
382  uint32_t tmp = value; /* make compiler warnings go away */
383  asm volatile ("EOR %1, %0, %0, ROR #16\n"
384                "BIC %1, %1, #0xff0000\n"
385                "MOV %0, %0, ROR #8\n"
386                "EOR %0, %0, %1, LSR #8\n"
387                : "=r" (value), "=r" (tmp)
388                : "0" (value), "1" (tmp));
389  return value;
390#endif
391}
392
393static inline uint16_t CPU_swap_u16( uint16_t value )
394{
395  return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU));
396}
397
398/** @} */
399
400/**
401 * @addtogroup ScoreCPUARM
402 *
403 * @{
404 */
405
406typedef struct {
407  uint32_t r0;
408  uint32_t r1;
409  uint32_t r2;
410  uint32_t r3;
411  uint32_t r4;
412  uint32_t r5;
413  uint32_t r6;
414  uint32_t r7;
415  uint32_t r8;
416  uint32_t r9;
417  uint32_t r10;
418  uint32_t r11;
419  uint32_t r12;
420  uint32_t sp;
421  uint32_t lr;
422  uint32_t pc;
423  uint32_t cpsr;
424} arm_cpu_context;
425
426typedef void arm_exc_abort_handler( arm_cpu_context *context );
427
428typedef enum {
429  ARM_EXCEPTION_RESET = 0,
430  ARM_EXCEPTION_UNDEF = 1,
431  ARM_EXCEPTION_SWI = 2,
432  ARM_EXCEPTION_PREF_ABORT = 3,
433  ARM_EXCEPTION_DATA_ABORT = 4,
434  ARM_EXCEPTION_RESERVED = 5,
435  ARM_EXCEPTION_IRQ = 6,
436  ARM_EXCEPTION_FIQ = 7,
437  MAX_EXCEPTIONS = 8
438} Arm_symbolic_exception_name;
439
440static inline uint32_t arm_status_irq_enable( void )
441{
442  uint32_t arm_switch_reg;
443  uint32_t psr;
444
445  RTEMS_COMPILER_MEMORY_BARRIER();
446
447  asm volatile (
448    ARM_SWITCH_TO_ARM
449    "mrs %[psr], cpsr\n"
450    "bic %[arm_switch_reg], %[psr], #0x80\n"
451    "msr cpsr, %[arm_switch_reg]\n"
452    ARM_SWITCH_BACK
453    : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr)
454  );
455
456  return psr;
457}
458
459static inline void arm_status_restore( uint32_t psr )
460{
461  ARM_SWITCH_REGISTERS;
462
463  asm volatile (
464    ARM_SWITCH_TO_ARM
465    "msr cpsr, %[psr]\n"
466    ARM_SWITCH_BACK
467    : ARM_SWITCH_OUTPUT
468    : [psr] "r" (psr)
469  );
470
471  RTEMS_COMPILER_MEMORY_BARRIER();
472}
473
474void arm_exc_data_abort_set_handler( arm_exc_abort_handler handler );
475
476void arm_exc_data_abort( void );
477
478void arm_exc_prefetch_abort_set_handler( arm_exc_abort_handler handler );
479
480void arm_exc_prefetch_abort( void );
481
482void bsp_interrupt_dispatch( void );
483
484void arm_exc_interrupt( void );
485
486void arm_exc_undefined( void );
487
488/** @} */
489
490/* XXX This is out of date */
491typedef struct {
492  uint32_t register_r0;
493  uint32_t register_r1;
494  uint32_t register_r2;
495  uint32_t register_r3;
496  uint32_t register_ip;
497  uint32_t register_lr;
498} CPU_Exception_frame;
499
500typedef CPU_Exception_frame CPU_Interrupt_frame;
501
502#ifdef __cplusplus
503}
504#endif
505
506#endif /* ASM */
507
508#endif /* _RTEMS_SCORE_CPU_H */
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