source: rtems/cpukit/score/cpu/arm/rtems/score/cpu.h @ 4848b56

4.104.11
Last change on this file since 4848b56 was 4848b56, checked in by Joel Sherrill <joel.sherrill@…>, on May 5, 2009 at 7:37:10 PM

2009-05-05 Joel Sherrill <joel.sherrill@…>

  • rtems/score/cpu.h: Remove warnings.
  • Property mode set to 100644
File size: 27.1 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 * $Id$
7 *
8 *  This include file contains information pertaining to the ARM
9 *  processor.
10 *
11 *  Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com>
12 *
13 *  Copyright (c) 2006 OAR Corporation
14 *
15 *  Copyright (c) 2002 Advent Networks, Inc.
16 *        Jay Monkman <jmonkman@adventnetworks.com>
17 *
18 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
19 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
20 *
21 *  The license and distribution terms for this file may be
22 *  found in the file LICENSE in this distribution or at
23 *  http://www.rtems.com/license/LICENSE.
24 *
25 */
26
27/* FIXME: finish commenting/cleaning up this file */
28#ifndef _RTEMS_SCORE_CPU_H
29#define _RTEMS_SCORE_CPU_H
30
31#ifdef __cplusplus
32extern "C" {
33#endif
34
35#include <rtems/score/arm.h>            /* pick up machine definitions */
36#ifndef ASM
37#include <rtems/score/types.h>
38#endif
39
40/* conditional compilation parameters */
41
42/*
43 *  Should the calls to _Thread_Enable_dispatch be inlined?
44 *
45 *  If TRUE, then they are inlined.
46 *  If FALSE, then a subroutine call is made.
47 *
48 *  Basically this is an example of the classic trade-off of size
49 *  versus speed.  Inlining the call (TRUE) typically increases the
50 *  size of RTEMS while speeding up the enabling of dispatching.
51 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
52 *  only be 0 or 1 unless you are in an interrupt handler and that
53 *  interrupt handler invokes the executive.]  When not inlined
54 *  something calls _Thread_Enable_dispatch which in turns calls
55 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
56 *  one subroutine call is avoided entirely.]
57 */
58
59#if defined(__thumb__)
60#define CPU_INLINE_ENABLE_DISPATCH       FALSE
61#else
62#define CPU_INLINE_ENABLE_DISPATCH       TRUE
63#endif
64
65/*
66 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
67 *  be unrolled one time?  In unrolled each iteration of the loop examines
68 *  two "nodes" on the chain being searched.  Otherwise, only one node
69 *  is examined per iteration.
70 *
71 *  If TRUE, then the loops are unrolled.
72 *  If FALSE, then the loops are not unrolled.
73 *
74 *  The primary factor in making this decision is the cost of disabling
75 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
76 *  body of the loop.  On some CPUs, the flash is more expensive than
77 *  one iteration of the loop body.  In this case, it might be desirable
78 *  to unroll the loop.  It is important to note that on some CPUs, this
79 *  code is the longest interrupt disable period in RTEMS.  So it is
80 *  necessary to strike a balance when setting this parameter.
81 */
82
83#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
84
85/*
86 *  Does RTEMS manage a dedicated interrupt stack in software?
87 *
88 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
89 *  If FALSE, nothing is done.
90 *
91 *  If the CPU supports a dedicated interrupt stack in hardware,
92 *  then it is generally the responsibility of the BSP to allocate it
93 *  and set it up.
94 *
95 *  If the CPU does not support a dedicated interrupt stack, then
96 *  the porter has two options: (1) execute interrupts on the
97 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
98 *  interrupt stack.
99 *
100 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
101 *
102 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
103 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
104 *  possible that both are FALSE for a particular CPU.  Although it
105 *  is unclear what that would imply about the interrupt processing
106 *  procedure on that CPU.
107 */
108
109#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
110
111/*
112 *  Does this CPU have hardware support for a dedicated interrupt stack?
113 *
114 *  If TRUE, then it must be installed during initialization.
115 *  If FALSE, then no installation is performed.
116 *
117 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
118 *
119 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
120 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
121 *  possible that both are FALSE for a particular CPU.  Although it
122 *  is unclear what that would imply about the interrupt processing
123 *  procedure on that CPU.
124 */
125
126#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
127
128/*
129 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
130 *
131 *  If TRUE, then the memory is allocated during initialization.
132 *  If FALSE, then the memory is allocated during initialization.
133 *
134 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
135 */
136
137#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
138
139/*
140 *  Does the RTEMS invoke the user's ISR with the vector number and
141 *  a pointer to the saved interrupt frame (1) or just the vector
142 *  number (0)?
143 */
144
145#define CPU_ISR_PASSES_FRAME_POINTER 0
146
147/*
148 *  Does the CPU have hardware floating point?
149 *
150 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
151 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
152 *
153 *  If there is a FP coprocessor such as the i387 or mc68881, then
154 *  the answer is TRUE.
155 *
156 *  The macro name "ARM_HAS_FPU" should be made CPU specific.
157 *  It indicates whether or not this CPU model has FP support.  For
158 *  example, it would be possible to have an i386_nofp CPU model
159 *  which set this to false to indicate that you have an i386 without
160 *  an i387 and wish to leave floating point support out of RTEMS.
161 */
162
163#if ( ARM_HAS_FPU == 1 )
164#define CPU_HARDWARE_FP     TRUE
165#else
166#define CPU_HARDWARE_FP     FALSE
167#endif
168
169#define CPU_SOFTWARE_FP     FALSE
170
171/*
172 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
173 *
174 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
175 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
176 *
177 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
178 */
179
180#define CPU_ALL_TASKS_ARE_FP     FALSE
181
182/*
183 *  Should the IDLE task have a floating point context?
184 *
185 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
186 *  and it has a floating point context which is switched in and out.
187 *  If FALSE, then the IDLE task does not have a floating point context.
188 *
189 *  Setting this to TRUE negatively impacts the time required to preempt
190 *  the IDLE task from an interrupt because the floating point context
191 *  must be saved as part of the preemption.
192 */
193
194#define CPU_IDLE_TASK_IS_FP      FALSE
195
196/*
197 *  Should the saving of the floating point registers be deferred
198 *  until a context switch is made to another different floating point
199 *  task?
200 *
201 *  If TRUE, then the floating point context will not be stored until
202 *  necessary.  It will remain in the floating point registers and not
203 *  disturned until another floating point task is switched to.
204 *
205 *  If FALSE, then the floating point context is saved when a floating
206 *  point task is switched out and restored when the next floating point
207 *  task is restored.  The state of the floating point registers between
208 *  those two operations is not specified.
209 *
210 *  If the floating point context does NOT have to be saved as part of
211 *  interrupt dispatching, then it should be safe to set this to TRUE.
212 *
213 *  Setting this flag to TRUE results in using a different algorithm
214 *  for deciding when to save and restore the floating point context.
215 *  The deferred FP switch algorithm minimizes the number of times
216 *  the FP context is saved and restored.  The FP context is not saved
217 *  until a context switch is made to another, different FP task.
218 *  Thus in a system with only one FP task, the FP context will never
219 *  be saved or restored.
220 */
221
222#define CPU_USE_DEFERRED_FP_SWITCH   FALSE
223
224/*
225 *  Does this port provide a CPU dependent IDLE task implementation?
226 *
227 *  If TRUE, then the routine _CPU_Thread_Idle_body
228 *  must be provided and is the default IDLE thread body instead of
229 *  _CPU_Thread_Idle_body.
230 *
231 *  If FALSE, then use the generic IDLE thread body if the BSP does
232 *  not provide one.
233 *
234 *  This is intended to allow for supporting processors which have
235 *  a low power or idle mode.  When the IDLE thread is executed, then
236 *  the CPU can be powered down.
237 *
238 *  The order of precedence for selecting the IDLE thread body is:
239 *
240 *    1.  BSP provided
241 *    2.  CPU dependent (if provided)
242 *    3.  generic (if no BSP and no CPU dependent)
243 */
244
245#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
246
247/*
248 *  Does the stack grow up (toward higher addresses) or down
249 *  (toward lower addresses)?
250 *
251 *  If TRUE, then the grows upward.
252 *  If FALSE, then the grows toward smaller addresses.
253 */
254
255#define CPU_STACK_GROWS_UP               FALSE
256
257/*
258 *  The following is the variable attribute used to force alignment
259 *  of critical RTEMS structures.  On some processors it may make
260 *  sense to have these aligned on tighter boundaries than
261 *  the minimum requirements of the compiler in order to have as
262 *  much of the critical data area as possible in a cache line.
263 *
264 *  The placement of this macro in the declaration of the variables
265 *  is based on the syntactically requirements of the GNU C
266 *  "__attribute__" extension.  For example with GNU C, use
267 *  the following to force a structures to a 32 byte boundary.
268 *
269 *      __attribute__ ((aligned (32)))
270 *
271 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
272 *         To benefit from using this, the data must be heavily
273 *         used so it will stay in the cache and used frequently enough
274 *         in the executive to justify turning this on.
275 */
276
277#define CPU_STRUCTURE_ALIGNMENT  __attribute__ ((aligned (32)))
278
279/*
280 *  Define what is required to specify how the network to host conversion
281 *  routines are handled.
282 */
283
284#if defined(__ARMEL__)
285#define CPU_BIG_ENDIAN          FALSE
286#define CPU_LITTLE_ENDIAN       TRUE
287#elif defined(__ARMEB__)
288#define CPU_BIG_ENDIAN          TRUE
289#define CPU_LITTLE_ENDIAN       FALSE
290#else
291#error "Unknown endianness"
292#endif
293                       
294/*
295 *  The following defines the number of bits actually used in the
296 *  interrupt field of the task mode.  How those bits map to the
297 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
298 */
299
300#define CPU_MODES_INTERRUPT_MASK   0x000000c0
301
302/*
303 *  Processor defined structures required by cpukit/score.
304 */
305
306/* may need to put some structures here.  */
307
308/*
309 * Contexts
310 *
311 *  Generally there are 2 types of context to save.
312 *     1. Interrupt registers to save
313 *     2. Task level registers to save
314 *
315 *  This means we have the following 3 context items:
316 *     1. task level context stuff::  Context_Control
317 *     2. floating point task stuff:: Context_Control_fp
318 *     3. special interrupt level context :: Context_Control_interrupt
319 *
320 *  On some processors, it is cost-effective to save only the callee
321 *  preserved registers during a task context switch.  This means
322 *  that the ISR code needs to save those registers which do not
323 *  persist across function calls.  It is not mandatory to make this
324 *  distinctions between the caller/callee saves registers for the
325 *  purpose of minimizing context saved during task switch and on interrupts.
326 *  If the cost of saving extra registers is minimal, simplicity is the
327 *  choice.  Save the same context on interrupt entry as for tasks in
328 *  this case.
329 *
330 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
331 *  care should be used in designing the context area.
332 *
333 *  On some CPUs with hardware floating point support, the Context_Control_fp
334 *  structure will not be used or it simply consist of an array of a
335 *  fixed number of bytes.   This is done when the floating point context
336 *  is dumped by a "FP save context" type instruction and the format
337 *  is not really defined by the CPU.  In this case, there is no need
338 *  to figure out the exact format -- only the size.  Of course, although
339 *  this is enough information for RTEMS, it is probably not enough for
340 *  a debugger such as gdb.  But that is another problem.
341 */
342typedef struct {
343    uint32_t   register_cpsr;
344    uint32_t   register_r4;
345    uint32_t   register_r5;
346    uint32_t   register_r6;
347    uint32_t   register_r7;
348    uint32_t   register_r8;
349    uint32_t   register_r9;
350    uint32_t   register_r10;
351    uint32_t   register_fp;
352    uint32_t   register_sp;
353    uint32_t   register_lr;
354    uint32_t   register_pc;
355} Context_Control;
356
357#define _CPU_Context_Get_SP( _context ) \
358  (_context)->register_sp
359
360typedef struct {
361    double      some_float_register;
362} Context_Control_fp;
363
364typedef struct {
365    uint32_t   register_r0;
366    uint32_t   register_r1;
367    uint32_t   register_r2;
368    uint32_t   register_r3;
369    uint32_t   register_ip;
370    uint32_t   register_lr;
371} CPU_Exception_frame;
372
373typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
374extern cpuExcHandlerType _currentExcHandler;
375extern void rtems_exception_init_mngt(void);
376 
377/*
378 *  The following structure defines the set of information saved
379 *  on the current stack by RTEMS upon receipt of each interrupt
380 *  that will lead to re-enter the kernel to signal the thread.
381 */
382
383typedef CPU_Exception_frame CPU_Interrupt_frame;
384
385/*
386 *  This variable is optional.  It is used on CPUs on which it is difficult
387 *  to generate an "uninitialized" FP context.  It is filled in by
388 *  _CPU_Initialize and copied into the task's FP context area during
389 *  _CPU_Context_Initialize.
390 */
391
392SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
393
394/*
395 *  The size of the floating point context area.  On some CPUs this
396 *  will not be a "sizeof" because the format of the floating point
397 *  area is not defined -- only the size is.  This is usually on
398 *  CPUs with a "floating point save context" instruction.
399 */
400
401#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
402
403/*
404 *  Amount of extra stack (above minimum stack size) required by
405 *  MPCI receive server thread.  Remember that in a multiprocessor
406 *  system this thread must exist and be able to process all directives.
407 */
408
409#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
410
411/*
412 *  This defines the number of entries in the ISR_Vector_table managed
413 *  by RTEMS.
414 */
415
416#define CPU_INTERRUPT_NUMBER_OF_VECTORS      8
417#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
418
419/*
420 *  This is defined if the port has a special way to report the ISR nesting
421 *  level.  Most ports maintain the variable _ISR_Nest_level.
422 */
423
424#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
425
426/*
427 *  Should be large enough to run all RTEMS tests.  This ensures
428 *  that a "reasonable" small application should not have any problems.
429 */
430
431#define CPU_STACK_MINIMUM_SIZE          (1024*4)
432
433/*
434 *  CPU's worst alignment requirement for data types on a byte boundary.  This
435 *  alignment does not take into account the requirements for the stack.
436 */
437
438#define CPU_ALIGNMENT              4
439
440/*
441 *  This number corresponds to the byte alignment requirement for the
442 *  heap handler.  This alignment requirement may be stricter than that
443 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
444 *  common for the heap to follow the same alignment requirement as
445 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
446 *  then this should be set to CPU_ALIGNMENT.
447 *
448 *  NOTE:  This does not have to be a power of 2.  It does have to
449 *         be greater or equal to than CPU_ALIGNMENT.
450 */
451
452#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
453
454/*
455 *  This number corresponds to the byte alignment requirement for memory
456 *  buffers allocated by the partition manager.  This alignment requirement
457 *  may be stricter than that for the data types alignment specified by
458 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
459 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
460 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
461 *
462 *  NOTE:  This does not have to be a power of 2.  It does have to
463 *         be greater or equal to than CPU_ALIGNMENT.
464 */
465
466#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
467
468/*
469 *  This number corresponds to the byte alignment requirement for the
470 *  stack.  This alignment requirement may be stricter than that for the
471 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
472 *  is strict enough for the stack, then this should be set to 0.
473 *
474 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
475 */
476
477#define CPU_STACK_ALIGNMENT        4
478
479/* ISR handler macros */
480
481/*
482 *  Support routine to initialize the RTEMS vector table after it is allocated.
483 */
484
485#define _CPU_Initialize_vectors()
486
487/*
488 *  Disable all interrupts for an RTEMS critical section.  The previous
489 *  level is returned in _level.
490 */
491#if (defined(__THUMB_INTERWORK__) || defined(__thumb__))
492
493extern uint32_t _CPU_ISR_Disable_Thumb(void) __attribute__ ((naked));
494extern void _CPU_ISR_Enable_Thumb( int ) __attribute__ ((naked));
495extern void _CPU_ISR_Flash_Thumb(int) __attribute__ ((naked));
496extern void _CPU_ISR_Set_level_Thumb(int ) __attribute__ ((naked));
497extern uint32_t _CPU_ISR_Get_level_Thumb(void ) __attribute__ ((naked));
498
499#define _CPU_ISR_Disable(_level)        \
500 (_level) = _CPU_ISR_Disable_Thumb()
501
502#define _CPU_ISR_Enable(a)      _CPU_ISR_Enable_Thumb(a)
503
504#define _CPU_ISR_Flash(a)       _CPU_ISR_Flash_Thumb(a)
505
506#define _CPU_ISR_Set_level(a)   _CPU_ISR_Set_level_Thumb(a)
507
508#define _CPU_ISR_Get_level(a)   _CPU_ISR_Get_level_Thumb(a)
509
510#else /*For ARM mode*/
511#define _CPU_ISR_Disable( _level )                \
512  {                                               \
513    int reg;                                       \
514    asm volatile ("MRS  %0, cpsr \n"               \
515                  "ORR  %1, %0, #0xc0 \n"          \
516                  "MSR  cpsr, %1 \n"               \
517                   : "=&r" (_level), "=&r" (reg)); \
518  }
519
520/*
521 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
522 *  This indicates the end of an RTEMS critical section.  The parameter
523 *  _level is not modified.
524 */
525
526#define _CPU_ISR_Enable( _level )               \
527  {                                             \
528    asm volatile ("MSR  cpsr, %0 \n"            \
529                  : : "r" (_level));            \
530  }
531
532/*
533 *  This temporarily restores the interrupt to _level before immediately
534 *  disabling them again.  This is used to divide long RTEMS critical
535 *  sections into two or more parts.  The parameter _level is not
536 * modified.
537 */
538
539#define _CPU_ISR_Flash( _level ) \
540  { \
541    int reg;                                    \
542    asm volatile ("MRS  %0, cpsr \n"            \
543                  "MSR  cpsr, %1 \n"            \
544                  "MSR  cpsr, %0 \n"            \
545                  : "=&r" (reg)                 \
546                  : "r" (_level));              \
547  }
548
549/*
550 *  Map interrupt level in task mode onto the hardware that the CPU
551 *  actually provides.  Currently, interrupt levels which do not
552 *  map onto the CPU in a generic fashion are undefined.  Someday,
553 *  it would be nice if these were "mapped" by the application
554 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
555 *  8 - 255 would be available for bsp/application specific meaning.
556 *  This could be used to manage a programmable interrupt controller
557 *  via the rtems_task_mode directive.
558 *
559 *  The get routine usually must be implemented as a subroutine.
560 */
561
562#define _CPU_ISR_Set_level( new_level )         \
563  {                                             \
564    int reg = 0; /* to avoid warning */         \
565    asm volatile ("MRS  %0, cpsr \n"            \
566                  "BIC  %0, %0, #0xc0 \n"       \
567                  "ORR  %0, %0, %2 \n"          \
568                  "MSR  cpsr_c, %0 \n"          \
569                  : "=r" (reg)                  \
570                  : "0" (reg), "r" (new_level)); \
571  }
572
573#endif /*(defined(__THUMB_INTERWORK__) || defined(__thumb__))*/
574
575uint32_t   _CPU_ISR_Get_level( void );
576
577/* end of ISR handler macros */
578
579/* Context handler macros */
580
581/*
582 *  Initialize the context to a state suitable for starting a
583 *  task after a context restore operation.  Generally, this
584 *  involves:
585 *
586 *     - setting a starting address
587 *     - preparing the stack
588 *     - preparing the stack and frame pointers
589 *     - setting the proper interrupt level in the context
590 *     - initializing the floating point context
591 *
592 *  This routine generally does not set any unnecessary register
593 *  in the context.  The state of the "general data" registers is
594 *  undefined at task start time.
595 *
596 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
597 *        point thread.  This is typically only used on CPUs where the
598 *        FPU may be easily disabled by software such as on the SPARC
599 *        where the PSR contains an enable FPU bit.
600 */
601
602void _CPU_Context_Initialize(
603  Context_Control  *the_context,
604  uint32_t         *stack_base,
605  uint32_t          size,
606  uint32_t          new_level,
607  void             *entry_point,
608  bool              is_fp
609);
610
611/*
612 *  This routine is responsible for somehow restarting the currently
613 *  executing task.  If you are lucky, then all that is necessary
614 *  is restoring the context.  Otherwise, there will need to be
615 *  a special assembly routine which does something special in this
616 *  case.  Context_Restore should work most of the time.  It will
617 *  not work if restarting self conflicts with the stack frame
618 *  assumptions of restoring a context.
619 */
620
621#define _CPU_Context_Restart_self( _the_context ) \
622   _CPU_Context_restore( (_the_context) );
623
624/*
625 *  The purpose of this macro is to allow the initial pointer into
626 *  a floating point context area (used to save the floating point
627 *  context) to be at an arbitrary place in the floating point
628 *  context area.
629 *
630 *  This is necessary because some FP units are designed to have
631 *  their context saved as a stack which grows into lower addresses.
632 *  Other FP units can be saved by simply moving registers into offsets
633 *  from the base of the context area.  Finally some FP units provide
634 *  a "dump context" instruction which could fill in from high to low
635 *  or low to high based on the whim of the CPU designers.
636 */
637
638#define _CPU_Context_Fp_start( _base, _offset ) \
639   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
640
641/*
642 *  This routine initializes the FP context area passed to it to.
643 *  There are a few standard ways in which to initialize the
644 *  floating point context.  The code included for this macro assumes
645 *  that this is a CPU in which a "initial" FP context was saved into
646 *  _CPU_Null_fp_context and it simply copies it to the destination
647 *  context passed to it.
648 *
649 *  Other models include (1) not doing anything, and (2) putting
650 *  a "null FP status word" in the correct place in the FP context.
651 */
652
653#define _CPU_Context_Initialize_fp( _destination ) \
654  { \
655   *(*(_destination)) = _CPU_Null_fp_context; \
656  }
657
658/* end of Context handler macros */
659
660/* Fatal Error manager macros */
661
662/*
663 *  This routine copies _error into a known place -- typically a stack
664 *  location or a register, optionally disables interrupts, and
665 *  halts/stops the CPU.
666 */
667
668#define _CPU_Fatal_halt( _error )           \
669   do {                                     \
670     int _level;                            \
671     _CPU_ISR_Disable( _level );            \
672     asm volatile ("mov r0, %0\n"           \
673                   : "=r" (_error)          \
674                   : "0" (_error)           \
675                   : "r0" );                \
676     while(1) ;                             \
677   } while(0);
678 
679
680/* end of Fatal Error manager macros */
681
682/* Bitfield handler macros */
683/*
684 * If we had a particularly fast function for finding the first
685 * bit set in a word, it would go here. Since we don't (*), we'll
686 * just use the universal macros.
687 *
688 * (*) On ARM V5 and later, there's a CLZ function which could be
689 *     used to implement much quicker than the default macro.
690 */
691#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
692#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
693
694/* functions */
695
696/*
697 *  _CPU_Initialize
698 *
699 *  This routine performs CPU dependent initialization.
700 */
701
702void _CPU_Initialize(void);
703
704typedef enum {
705  ARM_EXCEPTION_RESET      = 0,
706  ARM_EXCEPTION_UNDEF      = 1,
707  ARM_EXCEPTION_SWI        = 2,
708  ARM_EXCEPTION_PREF_ABORT = 3,
709  ARM_EXCEPTION_DATA_ABORT = 4,
710  ARM_EXCEPTION_RESERVED   = 5,
711  ARM_EXCEPTION_IRQ        = 6,
712  ARM_EXCEPTION_FIQ        = 7,
713  MAX_EXCEPTIONS           = 8
714} Arm_symbolic_exception_name;
715
716/*
717 *  _CPU_ISR_install_vector
718 *
719 *  This routine installs an interrupt vector.
720 */
721
722void _CPU_ISR_install_vector(
723  uint32_t    vector,
724  proc_ptr    new_handler,
725  proc_ptr   *old_handler
726);
727
728/*
729 *  _CPU_Install_interrupt_stack
730 *
731 *  This routine installs the hardware interrupt stack pointer.
732 *
733 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
734 *         is TRUE.
735 */
736
737void _CPU_Install_interrupt_stack( void );
738
739/*
740 *  _CPU_Context_switch
741 *
742 *  This routine switches from the run context to the heir context.
743 */
744
745void _CPU_Context_switch(
746  Context_Control  *run,
747  Context_Control  *heir
748);
749
750/*
751 *  _CPU_Context_restore
752 *
753 *  This routine is generally used only to restart self in an
754 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
755 *
756 *  NOTE: May be unnecessary to reload some registers.
757 */
758
759void _CPU_Context_restore(
760  Context_Control *new_context
761);
762
763#if (ARM_HAS_FPU == 1)
764/*
765 *  _CPU_Context_save_fp
766 *
767 *  This routine saves the floating point context passed to it.
768 */
769
770void _CPU_Context_save_fp(
771  Context_Control_fp **fp_context_ptr
772);
773
774/*
775 *  _CPU_Context_restore_fp
776 *
777 *  This routine restores the floating point context passed to it.
778 */
779
780void _CPU_Context_restore_fp(
781  Context_Control_fp **fp_context_ptr
782);
783#endif /* (ARM_HAS_FPU == 1) */
784
785/*  The following routine swaps the endian format of an unsigned int.
786 *  It must be static because it is referenced indirectly.
787 *
788 *  This version will work on any processor, but if there is a better
789 *  way for your CPU PLEASE use it.  The most common way to do this is to:
790 *
791 *     swap least significant two bytes with 16-bit rotate
792 *     swap upper and lower 16-bits
793 *     swap most significant two bytes with 16-bit rotate
794 *
795 *  Some CPUs have special instructions which swap a 32-bit quantity in
796 *  a single instruction (e.g. i486).  It is probably best to avoid
797 *  an "endian swapping control bit" in the CPU.  One good reason is
798 *  that interrupts would probably have to be disabled to ensure that
799 *  an interrupt does not try to access the same "chunk" with the wrong
800 *  endian.  Another good reason is that on some CPUs, the endian bit
801 *  endianness for ALL fetches -- both code and data -- so the code
802 *  will be fetched incorrectly.
803 */
804 
805static inline uint32_t CPU_swap_u32(
806  uint32_t value
807)
808{
809#if defined(__thumb__)
810  uint32_t byte1, byte2, byte3, byte4, swapped;
811 
812  byte4 = (value >> 24) & 0xff;
813  byte3 = (value >> 16) & 0xff;
814  byte2 = (value >> 8)  & 0xff;
815  byte1 =  value        & 0xff;
816 
817  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
818  return swapped;
819#else
820  uint32_t   tmp = value; /* make compiler warnings go away */
821  asm volatile ("EOR   %1, %0, %0, ROR #16\n" 
822                "BIC   %1, %1, #0xff0000\n"   
823                "MOV   %0, %0, ROR #8\n"     
824                "EOR   %0, %0, %1, LSR #8\n" 
825                : "=r" (value), "=r" (tmp) 
826                : "0" (value), "1" (tmp));
827  return value;
828#endif
829}
830
831static inline uint16_t CPU_swap_u16(uint16_t value)
832{
833    uint16_t   lower;
834    uint16_t   upper;
835
836    value = value & (uint16_t) 0xffff;
837    lower = (value >> 8);
838    upper = (value << 8) & 0xff;
839
840    return (lower | upper);
841}
842
843#ifdef __cplusplus
844}
845#endif
846
847#endif
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