[da215ded] | 1 | /** |
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[78623bce] | 2 | * @file |
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| 3 | * |
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[66fffc7] | 4 | * @brief ARM Architecture Support API |
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[da215ded] | 5 | */ |
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| 6 | |
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[4f0b287] | 7 | /* |
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| 8 | * This include file contains information pertaining to the ARM |
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[08330bf] | 9 | * processor. |
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| 10 | * |
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[8ae37323] | 11 | * Copyright (c) 2009-2014 embedded brains GmbH. |
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[39c8fdb] | 12 | * |
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[a3ff693] | 13 | * Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com> |
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| 14 | * |
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[6a07436] | 15 | * Copyright (c) 2006 OAR Corporation |
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| 16 | * |
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[fa237002] | 17 | * Copyright (c) 2002 Advent Networks, Inc. |
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[4f0b287] | 18 | * Jay Monkman <jmonkman@adventnetworks.com> |
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| 19 | * |
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[08330bf] | 20 | * COPYRIGHT (c) 2000 Canon Research Centre France SA. |
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| 21 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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| 22 | * |
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| 23 | * The license and distribution terms for this file may be |
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| 24 | * found in the file LICENSE in this distribution or at |
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[c499856] | 25 | * http://www.rtems.org/license/LICENSE. |
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[08330bf] | 26 | * |
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| 27 | */ |
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| 28 | |
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[7f70d1b7] | 29 | #ifndef _RTEMS_SCORE_CPU_H |
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| 30 | #define _RTEMS_SCORE_CPU_H |
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[08330bf] | 31 | |
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[89b85e51] | 32 | #include <rtems/score/types.h> |
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[632e4306] | 33 | #include <rtems/score/arm.h> |
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[08330bf] | 34 | |
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[c5ed148] | 35 | #if defined(ARM_MULTILIB_ARCH_V4) |
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| 36 | |
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[78623bce] | 37 | /** |
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| 38 | * @defgroup ScoreCPUARM ARM Specific Support |
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| 39 | * |
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| 40 | * @ingroup ScoreCPU |
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| 41 | * |
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| 42 | * @brief ARM specific support. |
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| 43 | */ |
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[b697bc6] | 44 | /**@{**/ |
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[78623bce] | 45 | |
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[2bbea4dd] | 46 | #if defined(__thumb__) && !defined(__thumb2__) |
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[39c8fdb] | 47 | #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg |
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| 48 | #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n" |
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| 49 | #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n" |
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| 50 | #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg) |
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| 51 | #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT |
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[248e29a] | 52 | #else |
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[39c8fdb] | 53 | #define ARM_SWITCH_REGISTERS |
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| 54 | #define ARM_SWITCH_TO_ARM |
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| 55 | #define ARM_SWITCH_BACK |
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| 56 | #define ARM_SWITCH_OUTPUT |
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| 57 | #define ARM_SWITCH_ADDITIONAL_OUTPUT |
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[248e29a] | 58 | #endif |
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[08330bf] | 59 | |
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[78623bce] | 60 | /** |
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| 61 | * @name Program Status Register |
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| 62 | */ |
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[b697bc6] | 63 | /**@{**/ |
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[78623bce] | 64 | |
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[39c8fdb] | 65 | #define ARM_PSR_N (1 << 31) |
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| 66 | #define ARM_PSR_Z (1 << 30) |
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| 67 | #define ARM_PSR_C (1 << 29) |
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| 68 | #define ARM_PSR_V (1 << 28) |
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| 69 | #define ARM_PSR_Q (1 << 27) |
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| 70 | #define ARM_PSR_J (1 << 24) |
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| 71 | #define ARM_PSR_GE_SHIFT 16 |
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| 72 | #define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT) |
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| 73 | #define ARM_PSR_E (1 << 9) |
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| 74 | #define ARM_PSR_A (1 << 8) |
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| 75 | #define ARM_PSR_I (1 << 7) |
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| 76 | #define ARM_PSR_F (1 << 6) |
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| 77 | #define ARM_PSR_T (1 << 5) |
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| 78 | #define ARM_PSR_M_SHIFT 0 |
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| 79 | #define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT) |
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| 80 | #define ARM_PSR_M_USR 0x10 |
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| 81 | #define ARM_PSR_M_FIQ 0x11 |
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| 82 | #define ARM_PSR_M_IRQ 0x12 |
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| 83 | #define ARM_PSR_M_SVC 0x13 |
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| 84 | #define ARM_PSR_M_ABT 0x17 |
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| 85 | #define ARM_PSR_M_UND 0x1b |
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| 86 | #define ARM_PSR_M_SYS 0x1f |
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| 87 | |
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[78623bce] | 88 | /** @} */ |
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| 89 | |
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| 90 | /** @} */ |
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| 91 | |
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[c5ed148] | 92 | #endif /* defined(ARM_MULTILIB_ARCH_V4) */ |
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| 93 | |
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[78623bce] | 94 | /** |
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| 95 | * @addtogroup ScoreCPU |
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| 96 | */ |
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[b697bc6] | 97 | /**@{**/ |
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[78623bce] | 98 | |
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[632e4306] | 99 | /* If someone uses THUMB we assume she wants minimal code size */ |
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| 100 | #ifdef __thumb__ |
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| 101 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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| 102 | #else |
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| 103 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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| 104 | #endif |
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[08330bf] | 105 | |
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[632e4306] | 106 | #if defined(__ARMEL__) |
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| 107 | #define CPU_BIG_ENDIAN FALSE |
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| 108 | #define CPU_LITTLE_ENDIAN TRUE |
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| 109 | #elif defined(__ARMEB__) |
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| 110 | #define CPU_BIG_ENDIAN TRUE |
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| 111 | #define CPU_LITTLE_ENDIAN FALSE |
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| 112 | #else |
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| 113 | #error "unknown endianness" |
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| 114 | #endif |
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[08330bf] | 115 | |
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[dea10503] | 116 | /* |
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| 117 | * The ARM uses the PIC interrupt model. |
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| 118 | */ |
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| 119 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
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| 120 | |
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[08330bf] | 121 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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| 122 | |
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[c5ed148] | 123 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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[08330bf] | 124 | |
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[fa237002] | 125 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
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[08330bf] | 126 | |
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| 127 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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| 128 | |
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[cfd8d7a] | 129 | #define CPU_HARDWARE_FP FALSE |
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[08330bf] | 130 | |
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[632e4306] | 131 | #define CPU_SOFTWARE_FP FALSE |
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[08330bf] | 132 | |
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[632e4306] | 133 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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[08330bf] | 134 | |
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[632e4306] | 135 | #define CPU_IDLE_TASK_IS_FP FALSE |
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[08330bf] | 136 | |
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[632e4306] | 137 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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[08330bf] | 138 | |
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[d9bd5cd6] | 139 | #if defined(ARM_MULTILIB_HAS_WFI) |
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[f4539aa] | 140 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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| 141 | #else |
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| 142 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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| 143 | #endif |
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[08330bf] | 144 | |
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[632e4306] | 145 | #define CPU_STACK_GROWS_UP FALSE |
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[08330bf] | 146 | |
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[632e4306] | 147 | /* XXX Why 32? */ |
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| 148 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) |
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[08330bf] | 149 | |
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[46689a1e] | 150 | #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE |
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[d0630763] | 151 | |
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[08330bf] | 152 | /* |
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[632e4306] | 153 | * The interrupt mask disables only normal interrupts (IRQ). |
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[08330bf] | 154 | * |
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[632e4306] | 155 | * In order to support fast interrupts (FIQ) such that they can do something |
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| 156 | * useful, we have to disable the operating system support for FIQs. Having |
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| 157 | * operating system support for them would require that FIQs are disabled |
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| 158 | * during critical sections of the operating system and application. At this |
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| 159 | * level IRQs and FIQs would be equal. It is true that FIQs could interrupt |
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| 160 | * the non critical sections of IRQs, so here they would have a small |
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| 161 | * advantage. Without operating system support, the FIQs can execute at any |
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| 162 | * time (of course not during the service of another FIQ). If someone needs |
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| 163 | * operating system support for a FIQ, she can trigger a software interrupt and |
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| 164 | * service the request in a two-step process. |
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[08330bf] | 165 | */ |
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[007bdc4] | 166 | #define CPU_MODES_INTERRUPT_MASK 0x1 |
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[08330bf] | 167 | |
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| 168 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 169 | |
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| 170 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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| 171 | |
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[4db30283] | 172 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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| 173 | |
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[632e4306] | 174 | #define CPU_STACK_MINIMUM_SIZE (1024 * 4) |
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[08330bf] | 175 | |
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[f1738ed] | 176 | /* AAPCS, section 4.1, Fundamental Data Types */ |
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| 177 | #define CPU_SIZEOF_POINTER 4 |
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| 178 | |
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[71c8457] | 179 | /* AAPCS, section 4.1, Fundamental Data Types */ |
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| 180 | #define CPU_ALIGNMENT 8 |
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[08330bf] | 181 | |
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[632e4306] | 182 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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[08330bf] | 183 | |
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[86820eda] | 184 | /* AAPCS, section 4.3.1, Aggregates */ |
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| 185 | #define CPU_PARTITION_ALIGNMENT 4 |
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[08330bf] | 186 | |
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[71c8457] | 187 | /* AAPCS, section 5.2.1.2, Stack constraints at a public interface */ |
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| 188 | #define CPU_STACK_ALIGNMENT 8 |
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[08330bf] | 189 | |
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| 190 | /* |
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[632e4306] | 191 | * Bitfield handler macros. |
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[08330bf] | 192 | * |
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[632e4306] | 193 | * If we had a particularly fast function for finding the first |
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| 194 | * bit set in a word, it would go here. Since we don't (*), we'll |
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| 195 | * just use the universal macros. |
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[08330bf] | 196 | * |
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[632e4306] | 197 | * (*) On ARM V5 and later, there's a CLZ function which could be |
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| 198 | * used to implement much quicker than the default macro. |
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[08330bf] | 199 | */ |
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| 200 | |
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[632e4306] | 201 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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[08330bf] | 202 | |
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[632e4306] | 203 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
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[08330bf] | 204 | |
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[10fd4aac] | 205 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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| 206 | |
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[78623bce] | 207 | /** @} */ |
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| 208 | |
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[022851a] | 209 | #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER |
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| 210 | #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44 |
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| 211 | #endif |
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| 212 | |
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[8ae37323] | 213 | #ifdef ARM_MULTILIB_VFP |
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[cfd8d7a] | 214 | #define ARM_CONTEXT_CONTROL_D8_OFFSET 48 |
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| 215 | #endif |
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| 216 | |
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[38b59a6] | 217 | #ifdef RTEMS_SMP |
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[8ae37323] | 218 | #ifdef ARM_MULTILIB_VFP |
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[38b59a6] | 219 | #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112 |
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| 220 | #else |
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| 221 | #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48 |
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| 222 | #endif |
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| 223 | #endif |
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| 224 | |
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[a6c5a7e0] | 225 | #define ARM_EXCEPTION_FRAME_SIZE 80 |
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[cfd8d7a] | 226 | |
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| 227 | #define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52 |
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| 228 | |
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| 229 | #define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72 |
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| 230 | |
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| 231 | #define ARM_VFP_CONTEXT_SIZE 264 |
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| 232 | |
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[632e4306] | 233 | #ifndef ASM |
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[2d877aa] | 234 | |
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[632e4306] | 235 | #ifdef __cplusplus |
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| 236 | extern "C" { |
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| 237 | #endif |
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[2d877aa] | 238 | |
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[78623bce] | 239 | /** |
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| 240 | * @addtogroup ScoreCPU |
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| 241 | */ |
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[b697bc6] | 242 | /**@{**/ |
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[661e5de4] | 243 | |
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[10fd4aac] | 244 | typedef struct { |
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| 245 | /* There is no CPU specific per-CPU state */ |
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| 246 | } CPU_Per_CPU_control; |
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| 247 | |
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[632e4306] | 248 | typedef struct { |
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[c5ed148] | 249 | #if defined(ARM_MULTILIB_ARCH_V4) |
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[632e4306] | 250 | uint32_t register_cpsr; |
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| 251 | uint32_t register_r4; |
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| 252 | uint32_t register_r5; |
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| 253 | uint32_t register_r6; |
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| 254 | uint32_t register_r7; |
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| 255 | uint32_t register_r8; |
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| 256 | uint32_t register_r9; |
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| 257 | uint32_t register_r10; |
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| 258 | uint32_t register_fp; |
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| 259 | uint32_t register_sp; |
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| 260 | uint32_t register_lr; |
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[5759510] | 261 | #elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) |
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[c5ed148] | 262 | uint32_t register_r4; |
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| 263 | uint32_t register_r5; |
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| 264 | uint32_t register_r6; |
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| 265 | uint32_t register_r7; |
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| 266 | uint32_t register_r8; |
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| 267 | uint32_t register_r9; |
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| 268 | uint32_t register_r10; |
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| 269 | uint32_t register_r11; |
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| 270 | void *register_lr; |
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| 271 | void *register_sp; |
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| 272 | uint32_t isr_nest_level; |
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[f442e6b4] | 273 | #else |
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| 274 | void *register_sp; |
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[c5ed148] | 275 | #endif |
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[022851a] | 276 | #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER |
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| 277 | uint32_t thread_id; |
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| 278 | #endif |
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[8ae37323] | 279 | #ifdef ARM_MULTILIB_VFP |
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[cfd8d7a] | 280 | uint64_t register_d8; |
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| 281 | uint64_t register_d9; |
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| 282 | uint64_t register_d10; |
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| 283 | uint64_t register_d11; |
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| 284 | uint64_t register_d12; |
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| 285 | uint64_t register_d13; |
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| 286 | uint64_t register_d14; |
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| 287 | uint64_t register_d15; |
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| 288 | #endif |
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[38b59a6] | 289 | #ifdef RTEMS_SMP |
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| 290 | volatile bool is_executing; |
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| 291 | #endif |
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[632e4306] | 292 | } Context_Control; |
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[661e5de4] | 293 | |
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[632e4306] | 294 | typedef struct { |
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| 295 | /* Not supported */ |
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| 296 | } Context_Control_fp; |
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[661e5de4] | 297 | |
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[78623bce] | 298 | extern uint32_t arm_cpu_mode; |
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| 299 | |
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[1a246d7e] | 300 | static inline void _ARM_Data_memory_barrier( void ) |
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| 301 | { |
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[7c90670] | 302 | #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS |
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[1a246d7e] | 303 | __asm__ volatile ( "dmb" : : : "memory" ); |
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[7c90670] | 304 | #endif |
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[1a246d7e] | 305 | } |
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| 306 | |
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| 307 | static inline void _ARM_Data_synchronization_barrier( void ) |
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| 308 | { |
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[7c90670] | 309 | #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS |
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[1a246d7e] | 310 | __asm__ volatile ( "dsb" : : : "memory" ); |
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[7c90670] | 311 | #endif |
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[1a246d7e] | 312 | } |
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| 313 | |
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| 314 | static inline void _ARM_Instruction_synchronization_barrier( void ) |
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| 315 | { |
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[7c90670] | 316 | #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS |
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[1a246d7e] | 317 | __asm__ volatile ( "isb" : : : "memory" ); |
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[7c90670] | 318 | #endif |
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[1a246d7e] | 319 | } |
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| 320 | |
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[632e4306] | 321 | static inline uint32_t arm_interrupt_disable( void ) |
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| 322 | { |
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[f442e6b4] | 323 | uint32_t level; |
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| 324 | |
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[c5ed148] | 325 | #if defined(ARM_MULTILIB_ARCH_V4) |
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[39c8fdb] | 326 | uint32_t arm_switch_reg; |
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[632e4306] | 327 | |
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[9f9371f] | 328 | __asm__ volatile ( |
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[39c8fdb] | 329 | ARM_SWITCH_TO_ARM |
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| 330 | "mrs %[level], cpsr\n" |
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| 331 | "orr %[arm_switch_reg], %[level], #0x80\n" |
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| 332 | "msr cpsr, %[arm_switch_reg]\n" |
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| 333 | ARM_SWITCH_BACK |
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| 334 | : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level) |
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[632e4306] | 335 | ); |
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[c5ed148] | 336 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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| 337 | uint32_t basepri = 0x80; |
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| 338 | |
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| 339 | __asm__ volatile ( |
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| 340 | "mrs %[level], basepri\n" |
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| 341 | "msr basepri_max, %[basepri]\n" |
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| 342 | : [level] "=&r" (level) |
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| 343 | : [basepri] "r" (basepri) |
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| 344 | ); |
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[f442e6b4] | 345 | #else |
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| 346 | level = 0; |
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| 347 | #endif |
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[c5ed148] | 348 | |
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| 349 | return level; |
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[632e4306] | 350 | } |
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[08330bf] | 351 | |
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[632e4306] | 352 | static inline void arm_interrupt_enable( uint32_t level ) |
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| 353 | { |
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[c5ed148] | 354 | #if defined(ARM_MULTILIB_ARCH_V4) |
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[39c8fdb] | 355 | ARM_SWITCH_REGISTERS; |
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| 356 | |
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[9f9371f] | 357 | __asm__ volatile ( |
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[39c8fdb] | 358 | ARM_SWITCH_TO_ARM |
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| 359 | "msr cpsr, %[level]\n" |
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| 360 | ARM_SWITCH_BACK |
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| 361 | : ARM_SWITCH_OUTPUT |
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| 362 | : [level] "r" (level) |
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| 363 | ); |
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[c5ed148] | 364 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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| 365 | __asm__ volatile ( |
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| 366 | "msr basepri, %[level]\n" |
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| 367 | : |
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| 368 | : [level] "r" (level) |
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| 369 | ); |
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| 370 | #endif |
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[632e4306] | 371 | } |
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[08330bf] | 372 | |
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[632e4306] | 373 | static inline void arm_interrupt_flash( uint32_t level ) |
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| 374 | { |
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[c5ed148] | 375 | #if defined(ARM_MULTILIB_ARCH_V4) |
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[39c8fdb] | 376 | uint32_t arm_switch_reg; |
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[632e4306] | 377 | |
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[9f9371f] | 378 | __asm__ volatile ( |
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[39c8fdb] | 379 | ARM_SWITCH_TO_ARM |
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| 380 | "mrs %[arm_switch_reg], cpsr\n" |
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| 381 | "msr cpsr, %[level]\n" |
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| 382 | "msr cpsr, %[arm_switch_reg]\n" |
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| 383 | ARM_SWITCH_BACK |
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| 384 | : [arm_switch_reg] "=&r" (arm_switch_reg) |
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| 385 | : [level] "r" (level) |
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[632e4306] | 386 | ); |
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[c5ed148] | 387 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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| 388 | uint32_t basepri; |
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| 389 | |
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| 390 | __asm__ volatile ( |
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| 391 | "mrs %[basepri], basepri\n" |
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| 392 | "msr basepri, %[level]\n" |
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| 393 | "msr basepri, %[basepri]\n" |
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| 394 | : [basepri] "=&r" (basepri) |
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| 395 | : [level] "r" (level) |
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| 396 | ); |
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| 397 | #endif |
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[632e4306] | 398 | } |
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[4f0b287] | 399 | |
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[632e4306] | 400 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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| 401 | do { \ |
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| 402 | _isr_cookie = arm_interrupt_disable(); \ |
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| 403 | } while (0) |
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[08330bf] | 404 | |
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[632e4306] | 405 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
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| 406 | arm_interrupt_enable( _isr_cookie ) |
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[08330bf] | 407 | |
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[632e4306] | 408 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
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| 409 | arm_interrupt_flash( _isr_cookie ) |
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[08330bf] | 410 | |
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[632e4306] | 411 | void _CPU_ISR_Set_level( uint32_t level ); |
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| 412 | |
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| 413 | uint32_t _CPU_ISR_Get_level( void ); |
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[08330bf] | 414 | |
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[4f0b287] | 415 | void _CPU_Context_Initialize( |
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[632e4306] | 416 | Context_Control *the_context, |
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[c5ed148] | 417 | void *stack_area_begin, |
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| 418 | size_t stack_area_size, |
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[632e4306] | 419 | uint32_t new_level, |
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[c5ed148] | 420 | void (*entry_point)( void ), |
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[022851a] | 421 | bool is_fp, |
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| 422 | void *tls_area |
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[4f0b287] | 423 | ); |
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[08330bf] | 424 | |
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[632e4306] | 425 | #define _CPU_Context_Get_SP( _context ) \ |
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| 426 | (_context)->register_sp |
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[08330bf] | 427 | |
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[38b59a6] | 428 | #ifdef RTEMS_SMP |
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[11b05f1] | 429 | static inline bool _CPU_Context_Get_is_executing( |
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| 430 | const Context_Control *context |
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| 431 | ) |
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| 432 | { |
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| 433 | return context->is_executing; |
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| 434 | } |
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| 435 | |
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| 436 | static inline void _CPU_Context_Set_is_executing( |
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| 437 | Context_Control *context, |
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| 438 | bool is_executing |
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| 439 | ) |
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| 440 | { |
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| 441 | context->is_executing = is_executing; |
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| 442 | } |
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[38b59a6] | 443 | #endif |
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| 444 | |
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[08330bf] | 445 | #define _CPU_Context_Restart_self( _the_context ) \ |
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| 446 | _CPU_Context_restore( (_the_context) ); |
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| 447 | |
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| 448 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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| 449 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
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| 450 | |
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| 451 | #define _CPU_Context_Initialize_fp( _destination ) \ |
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[632e4306] | 452 | do { \ |
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| 453 | *(*(_destination)) = _CPU_Null_fp_context; \ |
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| 454 | } while (0) |
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[08330bf] | 455 | |
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[f82752a4] | 456 | #define _CPU_Fatal_halt( _source, _err ) \ |
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[fa237002] | 457 | do { \ |
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[5e61c80] | 458 | uint32_t _level; \ |
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| 459 | uint32_t _error = _err; \ |
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[fa237002] | 460 | _CPU_ISR_Disable( _level ); \ |
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[f859d20] | 461 | (void) _level; \ |
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| 462 | __asm__ volatile ("mov r0, %0\n" \ |
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[fa237002] | 463 | : "=r" (_error) \ |
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| 464 | : "0" (_error) \ |
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| 465 | : "r0" ); \ |
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[632e4306] | 466 | while (1); \ |
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| 467 | } while (0); |
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[08330bf] | 468 | |
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[43e0599] | 469 | /** |
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[66fffc7] | 470 | * @brief CPU initialization. |
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[43e0599] | 471 | */ |
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[632e4306] | 472 | void _CPU_Initialize( void ); |
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[08330bf] | 473 | |
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| 474 | void _CPU_ISR_install_vector( |
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[632e4306] | 475 | uint32_t vector, |
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| 476 | proc_ptr new_handler, |
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| 477 | proc_ptr *old_handler |
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[08330bf] | 478 | ); |
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| 479 | |
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[43e0599] | 480 | /** |
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[66fffc7] | 481 | * @brief CPU switch context. |
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[43e0599] | 482 | */ |
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[632e4306] | 483 | void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); |
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[08330bf] | 484 | |
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[db0df7b] | 485 | void _CPU_Context_restore( Context_Control *new_context ) |
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[c5ed148] | 486 | RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
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| 487 | |
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| 488 | #if defined(ARM_MULTILIB_ARCH_V7M) |
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[bf19dbc3] | 489 | void _ARMV7M_Start_multitasking( Context_Control *heir ) |
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| 490 | RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
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[c5ed148] | 491 | #define _CPU_Start_multitasking _ARMV7M_Start_multitasking |
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| 492 | #endif |
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[08330bf] | 493 | |
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[39993d6] | 494 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
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| 495 | |
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| 496 | void _CPU_Context_validate( uintptr_t pattern ); |
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| 497 | |
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[f2f211c5] | 498 | #ifdef RTEMS_SMP |
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[53e008b] | 499 | uint32_t _CPU_SMP_Initialize( void ); |
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| 500 | |
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| 501 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
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| 502 | |
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| 503 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
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[4627fcd] | 504 | |
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[c34f94f7] | 505 | void _CPU_SMP_Prepare_start_multitasking( void ); |
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| 506 | |
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[47d60134] | 507 | static inline uint32_t _CPU_SMP_Get_current_processor( void ) |
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[39e51758] | 508 | { |
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| 509 | uint32_t mpidr; |
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| 510 | |
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| 511 | /* Use ARMv7 Multiprocessor Affinity Register (MPIDR) */ |
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[47d60134] | 512 | __asm__ volatile ( |
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[39e51758] | 513 | "mrc p15, 0, %[mpidr], c0, c0, 5\n" |
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| 514 | : [mpidr] "=&r" (mpidr) |
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| 515 | ); |
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| 516 | |
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| 517 | return mpidr & 0xffU; |
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| 518 | } |
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| 519 | |
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[ca63ae2] | 520 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
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| 521 | |
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[f2f211c5] | 522 | static inline void _ARM_Send_event( void ) |
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| 523 | { |
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| 524 | __asm__ volatile ( "sev" : : : "memory" ); |
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| 525 | } |
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| 526 | |
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| 527 | static inline void _ARM_Wait_for_event( void ) |
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| 528 | { |
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| 529 | __asm__ volatile ( "wfe" : : : "memory" ); |
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| 530 | } |
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| 531 | |
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[07f6e419] | 532 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
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[f2f211c5] | 533 | { |
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| 534 | _ARM_Data_synchronization_barrier(); |
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| 535 | _ARM_Send_event(); |
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| 536 | } |
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| 537 | |
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[f7740e97] | 538 | static inline void _CPU_SMP_Processor_event_receive( void ) |
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[f2f211c5] | 539 | { |
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| 540 | _ARM_Wait_for_event(); |
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| 541 | _ARM_Data_memory_barrier(); |
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| 542 | } |
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| 543 | #endif |
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| 544 | |
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| 545 | |
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[632e4306] | 546 | static inline uint32_t CPU_swap_u32( uint32_t value ) |
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[08330bf] | 547 | { |
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[c5ed148] | 548 | #if defined(__thumb2__) |
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| 549 | __asm__ volatile ( |
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| 550 | "rev %0, %0" |
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| 551 | : "=r" (value) |
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| 552 | : "0" (value) |
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| 553 | ); |
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| 554 | return value; |
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| 555 | #elif defined(__thumb__) |
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[1c62f169] | 556 | uint32_t byte1, byte2, byte3, byte4, swapped; |
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[632e4306] | 557 | |
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[1c62f169] | 558 | byte4 = (value >> 24) & 0xff; |
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| 559 | byte3 = (value >> 16) & 0xff; |
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| 560 | byte2 = (value >> 8) & 0xff; |
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[632e4306] | 561 | byte1 = value & 0xff; |
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| 562 | |
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[1c62f169] | 563 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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| 564 | return swapped; |
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| 565 | #else |
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[632e4306] | 566 | uint32_t tmp = value; /* make compiler warnings go away */ |
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[9f9371f] | 567 | __asm__ volatile ("EOR %1, %0, %0, ROR #16\n" |
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[632e4306] | 568 | "BIC %1, %1, #0xff0000\n" |
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| 569 | "MOV %0, %0, ROR #8\n" |
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| 570 | "EOR %0, %0, %1, LSR #8\n" |
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| 571 | : "=r" (value), "=r" (tmp) |
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[1c62f169] | 572 | : "0" (value), "1" (tmp)); |
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| 573 | return value; |
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| 574 | #endif |
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[08330bf] | 575 | } |
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| 576 | |
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[632e4306] | 577 | static inline uint16_t CPU_swap_u16( uint16_t value ) |
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[fa237002] | 578 | { |
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[c5ed148] | 579 | #if defined(__thumb2__) |
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| 580 | __asm__ volatile ( |
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| 581 | "rev16 %0, %0" |
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| 582 | : "=r" (value) |
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| 583 | : "0" (value) |
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| 584 | ); |
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| 585 | return value; |
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| 586 | #else |
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[632e4306] | 587 | return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU)); |
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[c5ed148] | 588 | #endif |
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[632e4306] | 589 | } |
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[b32fe793] | 590 | |
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[24bf11e] | 591 | typedef uint32_t CPU_Counter_ticks; |
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| 592 | |
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| 593 | CPU_Counter_ticks _CPU_Counter_read( void ); |
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| 594 | |
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| 595 | CPU_Counter_ticks _CPU_Counter_difference( |
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| 596 | CPU_Counter_ticks second, |
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| 597 | CPU_Counter_ticks first |
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| 598 | ); |
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| 599 | |
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[f4539aa] | 600 | #if CPU_PROVIDES_IDLE_THREAD_BODY == TRUE |
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| 601 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
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| 602 | #endif |
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| 603 | |
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[78623bce] | 604 | /** @} */ |
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[b32fe793] | 605 | |
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[78623bce] | 606 | /** |
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| 607 | * @addtogroup ScoreCPUARM |
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| 608 | */ |
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[b697bc6] | 609 | /**@{**/ |
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[632e4306] | 610 | |
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[0d8cde9] | 611 | #if defined(ARM_MULTILIB_ARCH_V4) |
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| 612 | |
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[78623bce] | 613 | typedef enum { |
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| 614 | ARM_EXCEPTION_RESET = 0, |
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| 615 | ARM_EXCEPTION_UNDEF = 1, |
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| 616 | ARM_EXCEPTION_SWI = 2, |
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| 617 | ARM_EXCEPTION_PREF_ABORT = 3, |
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| 618 | ARM_EXCEPTION_DATA_ABORT = 4, |
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| 619 | ARM_EXCEPTION_RESERVED = 5, |
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| 620 | ARM_EXCEPTION_IRQ = 6, |
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| 621 | ARM_EXCEPTION_FIQ = 7, |
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[8d687737] | 622 | MAX_EXCEPTIONS = 8, |
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| 623 | ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff |
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[78623bce] | 624 | } Arm_symbolic_exception_name; |
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| 625 | |
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[0d8cde9] | 626 | #endif /* defined(ARM_MULTILIB_ARCH_V4) */ |
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[78623bce] | 627 | |
---|
[cfd8d7a] | 628 | typedef struct { |
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| 629 | uint32_t register_fpexc; |
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| 630 | uint32_t register_fpscr; |
---|
| 631 | uint64_t register_d0; |
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| 632 | uint64_t register_d1; |
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| 633 | uint64_t register_d2; |
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| 634 | uint64_t register_d3; |
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| 635 | uint64_t register_d4; |
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| 636 | uint64_t register_d5; |
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| 637 | uint64_t register_d6; |
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| 638 | uint64_t register_d7; |
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| 639 | uint64_t register_d8; |
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| 640 | uint64_t register_d9; |
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| 641 | uint64_t register_d10; |
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| 642 | uint64_t register_d11; |
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| 643 | uint64_t register_d12; |
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| 644 | uint64_t register_d13; |
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| 645 | uint64_t register_d14; |
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| 646 | uint64_t register_d15; |
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| 647 | uint64_t register_d16; |
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| 648 | uint64_t register_d17; |
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| 649 | uint64_t register_d18; |
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| 650 | uint64_t register_d19; |
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| 651 | uint64_t register_d20; |
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| 652 | uint64_t register_d21; |
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| 653 | uint64_t register_d22; |
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| 654 | uint64_t register_d23; |
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| 655 | uint64_t register_d24; |
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| 656 | uint64_t register_d25; |
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| 657 | uint64_t register_d26; |
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| 658 | uint64_t register_d27; |
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| 659 | uint64_t register_d28; |
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| 660 | uint64_t register_d29; |
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| 661 | uint64_t register_d30; |
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| 662 | uint64_t register_d31; |
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| 663 | } ARM_VFP_context; |
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| 664 | |
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[78623bce] | 665 | typedef struct { |
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| 666 | uint32_t register_r0; |
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| 667 | uint32_t register_r1; |
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| 668 | uint32_t register_r2; |
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| 669 | uint32_t register_r3; |
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[8d687737] | 670 | uint32_t register_r4; |
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| 671 | uint32_t register_r5; |
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| 672 | uint32_t register_r6; |
---|
| 673 | uint32_t register_r7; |
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| 674 | uint32_t register_r8; |
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| 675 | uint32_t register_r9; |
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| 676 | uint32_t register_r10; |
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| 677 | uint32_t register_r11; |
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| 678 | uint32_t register_r12; |
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| 679 | uint32_t register_sp; |
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[0d8cde9] | 680 | void *register_lr; |
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| 681 | void *register_pc; |
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| 682 | #if defined(ARM_MULTILIB_ARCH_V4) |
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[8d687737] | 683 | uint32_t register_cpsr; |
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| 684 | Arm_symbolic_exception_name vector; |
---|
[5759510] | 685 | #elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) |
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[0d8cde9] | 686 | uint32_t register_xpsr; |
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| 687 | uint32_t vector; |
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| 688 | #endif |
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[cfd8d7a] | 689 | const ARM_VFP_context *vfp_context; |
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[a6c5a7e0] | 690 | uint32_t reserved_for_stack_alignment; |
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[78623bce] | 691 | } CPU_Exception_frame; |
---|
| 692 | |
---|
| 693 | typedef CPU_Exception_frame CPU_Interrupt_frame; |
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| 694 | |
---|
[815994f] | 695 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
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| 696 | |
---|
[50f3c42b] | 697 | void _ARM_Exception_default( CPU_Exception_frame *frame ); |
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| 698 | |
---|
[037b57a] | 699 | /* |
---|
| 700 | * FIXME: In case your BSP uses this function, then convert it to use |
---|
| 701 | * the shared start.S file for ARM. |
---|
| 702 | */ |
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| 703 | void rtems_exception_init_mngt( void ); |
---|
| 704 | |
---|
[0d8cde9] | 705 | /** @} */ |
---|
| 706 | |
---|
[08330bf] | 707 | #ifdef __cplusplus |
---|
| 708 | } |
---|
| 709 | #endif |
---|
| 710 | |
---|
[632e4306] | 711 | #endif /* ASM */ |
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| 712 | |
---|
| 713 | #endif /* _RTEMS_SCORE_CPU_H */ |
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