[da215ded] | 1 | /** |
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[78623bce] | 2 | * @file |
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| 3 | * |
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[66fffc7] | 4 | * @brief ARM Architecture Support API |
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[da215ded] | 5 | */ |
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| 6 | |
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[4f0b287] | 7 | /* |
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| 8 | * This include file contains information pertaining to the ARM |
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[08330bf] | 9 | * processor. |
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| 10 | * |
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[cfd8d7a] | 11 | * Copyright (c) 2009-2013 embedded brains GmbH. |
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[39c8fdb] | 12 | * |
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[a3ff693] | 13 | * Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com> |
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| 14 | * |
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[6a07436] | 15 | * Copyright (c) 2006 OAR Corporation |
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| 16 | * |
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[fa237002] | 17 | * Copyright (c) 2002 Advent Networks, Inc. |
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[4f0b287] | 18 | * Jay Monkman <jmonkman@adventnetworks.com> |
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| 19 | * |
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[08330bf] | 20 | * COPYRIGHT (c) 2000 Canon Research Centre France SA. |
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| 21 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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| 22 | * |
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| 23 | * The license and distribution terms for this file may be |
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| 24 | * found in the file LICENSE in this distribution or at |
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[c499856] | 25 | * http://www.rtems.org/license/LICENSE. |
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[08330bf] | 26 | * |
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| 27 | */ |
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| 28 | |
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[7f70d1b7] | 29 | #ifndef _RTEMS_SCORE_CPU_H |
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| 30 | #define _RTEMS_SCORE_CPU_H |
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[08330bf] | 31 | |
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[89b85e51] | 32 | #include <rtems/score/types.h> |
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[632e4306] | 33 | #include <rtems/score/arm.h> |
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[08330bf] | 34 | |
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[c5ed148] | 35 | #if defined(ARM_MULTILIB_ARCH_V4) |
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| 36 | |
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[78623bce] | 37 | /** |
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| 38 | * @defgroup ScoreCPUARM ARM Specific Support |
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| 39 | * |
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| 40 | * @ingroup ScoreCPU |
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| 41 | * |
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| 42 | * @brief ARM specific support. |
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| 43 | */ |
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[b697bc6] | 44 | /**@{**/ |
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[78623bce] | 45 | |
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[2bbea4dd] | 46 | #if defined(__thumb__) && !defined(__thumb2__) |
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[39c8fdb] | 47 | #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg |
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| 48 | #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n" |
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| 49 | #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n" |
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| 50 | #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg) |
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| 51 | #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT |
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[248e29a] | 52 | #else |
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[39c8fdb] | 53 | #define ARM_SWITCH_REGISTERS |
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| 54 | #define ARM_SWITCH_TO_ARM |
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| 55 | #define ARM_SWITCH_BACK |
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| 56 | #define ARM_SWITCH_OUTPUT |
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| 57 | #define ARM_SWITCH_ADDITIONAL_OUTPUT |
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[248e29a] | 58 | #endif |
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[08330bf] | 59 | |
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[78623bce] | 60 | /** |
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| 61 | * @name Program Status Register |
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| 62 | */ |
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[b697bc6] | 63 | /**@{**/ |
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[78623bce] | 64 | |
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[39c8fdb] | 65 | #define ARM_PSR_N (1 << 31) |
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| 66 | #define ARM_PSR_Z (1 << 30) |
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| 67 | #define ARM_PSR_C (1 << 29) |
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| 68 | #define ARM_PSR_V (1 << 28) |
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| 69 | #define ARM_PSR_Q (1 << 27) |
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| 70 | #define ARM_PSR_J (1 << 24) |
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| 71 | #define ARM_PSR_GE_SHIFT 16 |
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| 72 | #define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT) |
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| 73 | #define ARM_PSR_E (1 << 9) |
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| 74 | #define ARM_PSR_A (1 << 8) |
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| 75 | #define ARM_PSR_I (1 << 7) |
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| 76 | #define ARM_PSR_F (1 << 6) |
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| 77 | #define ARM_PSR_T (1 << 5) |
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| 78 | #define ARM_PSR_M_SHIFT 0 |
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| 79 | #define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT) |
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| 80 | #define ARM_PSR_M_USR 0x10 |
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| 81 | #define ARM_PSR_M_FIQ 0x11 |
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| 82 | #define ARM_PSR_M_IRQ 0x12 |
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| 83 | #define ARM_PSR_M_SVC 0x13 |
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| 84 | #define ARM_PSR_M_ABT 0x17 |
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| 85 | #define ARM_PSR_M_UND 0x1b |
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| 86 | #define ARM_PSR_M_SYS 0x1f |
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| 87 | |
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[78623bce] | 88 | /** @} */ |
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| 89 | |
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| 90 | /** @} */ |
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| 91 | |
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[c5ed148] | 92 | #endif /* defined(ARM_MULTILIB_ARCH_V4) */ |
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| 93 | |
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[78623bce] | 94 | /** |
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| 95 | * @addtogroup ScoreCPU |
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| 96 | */ |
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[b697bc6] | 97 | /**@{**/ |
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[78623bce] | 98 | |
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[632e4306] | 99 | /* If someone uses THUMB we assume she wants minimal code size */ |
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| 100 | #ifdef __thumb__ |
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| 101 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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| 102 | #else |
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| 103 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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| 104 | #endif |
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[08330bf] | 105 | |
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[632e4306] | 106 | #if defined(__ARMEL__) |
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| 107 | #define CPU_BIG_ENDIAN FALSE |
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| 108 | #define CPU_LITTLE_ENDIAN TRUE |
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| 109 | #elif defined(__ARMEB__) |
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| 110 | #define CPU_BIG_ENDIAN TRUE |
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| 111 | #define CPU_LITTLE_ENDIAN FALSE |
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| 112 | #else |
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| 113 | #error "unknown endianness" |
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| 114 | #endif |
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[08330bf] | 115 | |
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[632e4306] | 116 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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[08330bf] | 117 | |
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[dea10503] | 118 | /* |
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| 119 | * The ARM uses the PIC interrupt model. |
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| 120 | */ |
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| 121 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
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| 122 | |
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[08330bf] | 123 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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| 124 | |
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[c5ed148] | 125 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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[08330bf] | 126 | |
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[fa237002] | 127 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
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[08330bf] | 128 | |
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| 129 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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| 130 | |
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[cfd8d7a] | 131 | #define CPU_HARDWARE_FP FALSE |
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[08330bf] | 132 | |
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[632e4306] | 133 | #define CPU_SOFTWARE_FP FALSE |
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[08330bf] | 134 | |
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[632e4306] | 135 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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[08330bf] | 136 | |
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[632e4306] | 137 | #define CPU_IDLE_TASK_IS_FP FALSE |
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[08330bf] | 138 | |
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[632e4306] | 139 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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[08330bf] | 140 | |
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[d9bd5cd6] | 141 | #if defined(ARM_MULTILIB_HAS_WFI) |
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[f4539aa] | 142 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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| 143 | #else |
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| 144 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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| 145 | #endif |
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[08330bf] | 146 | |
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[632e4306] | 147 | #define CPU_STACK_GROWS_UP FALSE |
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[08330bf] | 148 | |
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[632e4306] | 149 | /* XXX Why 32? */ |
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| 150 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) |
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[08330bf] | 151 | |
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[d0630763] | 152 | #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE |
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| 153 | |
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[08330bf] | 154 | /* |
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[632e4306] | 155 | * The interrupt mask disables only normal interrupts (IRQ). |
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[08330bf] | 156 | * |
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[632e4306] | 157 | * In order to support fast interrupts (FIQ) such that they can do something |
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| 158 | * useful, we have to disable the operating system support for FIQs. Having |
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| 159 | * operating system support for them would require that FIQs are disabled |
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| 160 | * during critical sections of the operating system and application. At this |
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| 161 | * level IRQs and FIQs would be equal. It is true that FIQs could interrupt |
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| 162 | * the non critical sections of IRQs, so here they would have a small |
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| 163 | * advantage. Without operating system support, the FIQs can execute at any |
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| 164 | * time (of course not during the service of another FIQ). If someone needs |
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| 165 | * operating system support for a FIQ, she can trigger a software interrupt and |
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| 166 | * service the request in a two-step process. |
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[08330bf] | 167 | */ |
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[007bdc4] | 168 | #define CPU_MODES_INTERRUPT_MASK 0x1 |
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[08330bf] | 169 | |
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| 170 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 171 | |
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| 172 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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| 173 | |
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[632e4306] | 174 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 8 |
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[08330bf] | 175 | |
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[632e4306] | 176 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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[4db30283] | 177 | |
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| 178 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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| 179 | |
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[632e4306] | 180 | #define CPU_STACK_MINIMUM_SIZE (1024 * 4) |
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[08330bf] | 181 | |
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[f1738ed] | 182 | /* AAPCS, section 4.1, Fundamental Data Types */ |
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| 183 | #define CPU_SIZEOF_POINTER 4 |
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| 184 | |
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[71c8457] | 185 | /* AAPCS, section 4.1, Fundamental Data Types */ |
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| 186 | #define CPU_ALIGNMENT 8 |
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[08330bf] | 187 | |
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[632e4306] | 188 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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[08330bf] | 189 | |
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[86820eda] | 190 | /* AAPCS, section 4.3.1, Aggregates */ |
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| 191 | #define CPU_PARTITION_ALIGNMENT 4 |
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[08330bf] | 192 | |
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[71c8457] | 193 | /* AAPCS, section 5.2.1.2, Stack constraints at a public interface */ |
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| 194 | #define CPU_STACK_ALIGNMENT 8 |
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[08330bf] | 195 | |
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| 196 | /* |
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[632e4306] | 197 | * Bitfield handler macros. |
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[08330bf] | 198 | * |
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[632e4306] | 199 | * If we had a particularly fast function for finding the first |
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| 200 | * bit set in a word, it would go here. Since we don't (*), we'll |
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| 201 | * just use the universal macros. |
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[08330bf] | 202 | * |
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[632e4306] | 203 | * (*) On ARM V5 and later, there's a CLZ function which could be |
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| 204 | * used to implement much quicker than the default macro. |
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[08330bf] | 205 | */ |
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| 206 | |
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[632e4306] | 207 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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[08330bf] | 208 | |
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[632e4306] | 209 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
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[08330bf] | 210 | |
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[10fd4aac] | 211 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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| 212 | |
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[78623bce] | 213 | /** @} */ |
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| 214 | |
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[022851a] | 215 | #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER |
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| 216 | #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44 |
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| 217 | #endif |
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| 218 | |
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[cfd8d7a] | 219 | #ifdef ARM_MULTILIB_VFP_D32 |
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| 220 | #define ARM_CONTEXT_CONTROL_D8_OFFSET 48 |
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| 221 | #endif |
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| 222 | |
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| 223 | #define ARM_EXCEPTION_FRAME_SIZE 76 |
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| 224 | |
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| 225 | #define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52 |
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| 226 | |
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| 227 | #define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72 |
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| 228 | |
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| 229 | #define ARM_VFP_CONTEXT_SIZE 264 |
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| 230 | |
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[632e4306] | 231 | #ifndef ASM |
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[2d877aa] | 232 | |
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[632e4306] | 233 | #ifdef __cplusplus |
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| 234 | extern "C" { |
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| 235 | #endif |
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[2d877aa] | 236 | |
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[78623bce] | 237 | /** |
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| 238 | * @addtogroup ScoreCPU |
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| 239 | */ |
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[b697bc6] | 240 | /**@{**/ |
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[661e5de4] | 241 | |
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[10fd4aac] | 242 | typedef struct { |
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| 243 | /* There is no CPU specific per-CPU state */ |
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| 244 | } CPU_Per_CPU_control; |
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| 245 | |
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[632e4306] | 246 | typedef struct { |
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[c5ed148] | 247 | #if defined(ARM_MULTILIB_ARCH_V4) |
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[632e4306] | 248 | uint32_t register_cpsr; |
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| 249 | uint32_t register_r4; |
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| 250 | uint32_t register_r5; |
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| 251 | uint32_t register_r6; |
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| 252 | uint32_t register_r7; |
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| 253 | uint32_t register_r8; |
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| 254 | uint32_t register_r9; |
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| 255 | uint32_t register_r10; |
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| 256 | uint32_t register_fp; |
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| 257 | uint32_t register_sp; |
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| 258 | uint32_t register_lr; |
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[c5ed148] | 259 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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| 260 | uint32_t register_r4; |
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| 261 | uint32_t register_r5; |
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| 262 | uint32_t register_r6; |
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| 263 | uint32_t register_r7; |
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| 264 | uint32_t register_r8; |
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| 265 | uint32_t register_r9; |
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| 266 | uint32_t register_r10; |
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| 267 | uint32_t register_r11; |
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| 268 | void *register_lr; |
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| 269 | void *register_sp; |
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| 270 | uint32_t isr_nest_level; |
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[f442e6b4] | 271 | #else |
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| 272 | void *register_sp; |
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[c5ed148] | 273 | #endif |
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[022851a] | 274 | #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER |
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| 275 | uint32_t thread_id; |
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| 276 | #endif |
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[cfd8d7a] | 277 | #ifdef ARM_MULTILIB_VFP_D32 |
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| 278 | uint64_t register_d8; |
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| 279 | uint64_t register_d9; |
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| 280 | uint64_t register_d10; |
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| 281 | uint64_t register_d11; |
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| 282 | uint64_t register_d12; |
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| 283 | uint64_t register_d13; |
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| 284 | uint64_t register_d14; |
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| 285 | uint64_t register_d15; |
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| 286 | #endif |
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[632e4306] | 287 | } Context_Control; |
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[661e5de4] | 288 | |
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[632e4306] | 289 | typedef struct { |
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| 290 | /* Not supported */ |
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| 291 | } Context_Control_fp; |
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[661e5de4] | 292 | |
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[78623bce] | 293 | extern uint32_t arm_cpu_mode; |
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| 294 | |
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[1a246d7e] | 295 | static inline void _ARM_Data_memory_barrier( void ) |
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| 296 | { |
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| 297 | __asm__ volatile ( "dmb" : : : "memory" ); |
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| 298 | } |
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| 299 | |
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| 300 | static inline void _ARM_Data_synchronization_barrier( void ) |
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| 301 | { |
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| 302 | __asm__ volatile ( "dsb" : : : "memory" ); |
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| 303 | } |
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| 304 | |
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| 305 | static inline void _ARM_Instruction_synchronization_barrier( void ) |
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| 306 | { |
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| 307 | __asm__ volatile ( "isb" : : : "memory" ); |
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| 308 | } |
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| 309 | |
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[632e4306] | 310 | static inline uint32_t arm_interrupt_disable( void ) |
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| 311 | { |
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[f442e6b4] | 312 | uint32_t level; |
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| 313 | |
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[c5ed148] | 314 | #if defined(ARM_MULTILIB_ARCH_V4) |
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[39c8fdb] | 315 | uint32_t arm_switch_reg; |
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[632e4306] | 316 | |
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[9f9371f] | 317 | __asm__ volatile ( |
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[39c8fdb] | 318 | ARM_SWITCH_TO_ARM |
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| 319 | "mrs %[level], cpsr\n" |
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| 320 | "orr %[arm_switch_reg], %[level], #0x80\n" |
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| 321 | "msr cpsr, %[arm_switch_reg]\n" |
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| 322 | ARM_SWITCH_BACK |
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| 323 | : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level) |
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[632e4306] | 324 | ); |
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[c5ed148] | 325 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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| 326 | uint32_t basepri = 0x80; |
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| 327 | |
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| 328 | __asm__ volatile ( |
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| 329 | "mrs %[level], basepri\n" |
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| 330 | "msr basepri_max, %[basepri]\n" |
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| 331 | : [level] "=&r" (level) |
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| 332 | : [basepri] "r" (basepri) |
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| 333 | ); |
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[f442e6b4] | 334 | #else |
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| 335 | level = 0; |
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| 336 | #endif |
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[c5ed148] | 337 | |
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| 338 | return level; |
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[632e4306] | 339 | } |
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[08330bf] | 340 | |
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[632e4306] | 341 | static inline void arm_interrupt_enable( uint32_t level ) |
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| 342 | { |
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[c5ed148] | 343 | #if defined(ARM_MULTILIB_ARCH_V4) |
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[39c8fdb] | 344 | ARM_SWITCH_REGISTERS; |
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| 345 | |
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[9f9371f] | 346 | __asm__ volatile ( |
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[39c8fdb] | 347 | ARM_SWITCH_TO_ARM |
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| 348 | "msr cpsr, %[level]\n" |
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| 349 | ARM_SWITCH_BACK |
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| 350 | : ARM_SWITCH_OUTPUT |
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| 351 | : [level] "r" (level) |
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| 352 | ); |
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[c5ed148] | 353 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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| 354 | __asm__ volatile ( |
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| 355 | "msr basepri, %[level]\n" |
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| 356 | : |
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| 357 | : [level] "r" (level) |
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| 358 | ); |
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| 359 | #endif |
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[632e4306] | 360 | } |
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[08330bf] | 361 | |
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[632e4306] | 362 | static inline void arm_interrupt_flash( uint32_t level ) |
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| 363 | { |
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[c5ed148] | 364 | #if defined(ARM_MULTILIB_ARCH_V4) |
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[39c8fdb] | 365 | uint32_t arm_switch_reg; |
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[632e4306] | 366 | |
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[9f9371f] | 367 | __asm__ volatile ( |
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[39c8fdb] | 368 | ARM_SWITCH_TO_ARM |
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| 369 | "mrs %[arm_switch_reg], cpsr\n" |
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| 370 | "msr cpsr, %[level]\n" |
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| 371 | "msr cpsr, %[arm_switch_reg]\n" |
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| 372 | ARM_SWITCH_BACK |
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| 373 | : [arm_switch_reg] "=&r" (arm_switch_reg) |
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| 374 | : [level] "r" (level) |
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[632e4306] | 375 | ); |
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[c5ed148] | 376 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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| 377 | uint32_t basepri; |
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| 378 | |
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| 379 | __asm__ volatile ( |
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| 380 | "mrs %[basepri], basepri\n" |
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| 381 | "msr basepri, %[level]\n" |
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| 382 | "msr basepri, %[basepri]\n" |
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| 383 | : [basepri] "=&r" (basepri) |
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| 384 | : [level] "r" (level) |
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| 385 | ); |
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| 386 | #endif |
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[632e4306] | 387 | } |
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[4f0b287] | 388 | |
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[632e4306] | 389 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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| 390 | do { \ |
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| 391 | _isr_cookie = arm_interrupt_disable(); \ |
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| 392 | } while (0) |
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[08330bf] | 393 | |
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[632e4306] | 394 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
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| 395 | arm_interrupt_enable( _isr_cookie ) |
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[08330bf] | 396 | |
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[632e4306] | 397 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
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| 398 | arm_interrupt_flash( _isr_cookie ) |
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[08330bf] | 399 | |
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[632e4306] | 400 | void _CPU_ISR_Set_level( uint32_t level ); |
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| 401 | |
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| 402 | uint32_t _CPU_ISR_Get_level( void ); |
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[08330bf] | 403 | |
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[4f0b287] | 404 | void _CPU_Context_Initialize( |
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[632e4306] | 405 | Context_Control *the_context, |
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[c5ed148] | 406 | void *stack_area_begin, |
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| 407 | size_t stack_area_size, |
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[632e4306] | 408 | uint32_t new_level, |
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[c5ed148] | 409 | void (*entry_point)( void ), |
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[022851a] | 410 | bool is_fp, |
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| 411 | void *tls_area |
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[4f0b287] | 412 | ); |
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[08330bf] | 413 | |
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[632e4306] | 414 | #define _CPU_Context_Get_SP( _context ) \ |
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| 415 | (_context)->register_sp |
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[08330bf] | 416 | |
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| 417 | #define _CPU_Context_Restart_self( _the_context ) \ |
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| 418 | _CPU_Context_restore( (_the_context) ); |
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| 419 | |
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| 420 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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| 421 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
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| 422 | |
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| 423 | #define _CPU_Context_Initialize_fp( _destination ) \ |
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[632e4306] | 424 | do { \ |
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| 425 | *(*(_destination)) = _CPU_Null_fp_context; \ |
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| 426 | } while (0) |
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[08330bf] | 427 | |
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[5e61c80] | 428 | #define _CPU_Fatal_halt( _err ) \ |
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[fa237002] | 429 | do { \ |
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[5e61c80] | 430 | uint32_t _level; \ |
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| 431 | uint32_t _error = _err; \ |
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[fa237002] | 432 | _CPU_ISR_Disable( _level ); \ |
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[f859d20] | 433 | (void) _level; \ |
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| 434 | __asm__ volatile ("mov r0, %0\n" \ |
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[fa237002] | 435 | : "=r" (_error) \ |
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| 436 | : "0" (_error) \ |
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| 437 | : "r0" ); \ |
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[632e4306] | 438 | while (1); \ |
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| 439 | } while (0); |
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[08330bf] | 440 | |
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[43e0599] | 441 | /** |
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[66fffc7] | 442 | * @brief CPU initialization. |
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[43e0599] | 443 | */ |
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[632e4306] | 444 | void _CPU_Initialize( void ); |
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[08330bf] | 445 | |
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| 446 | void _CPU_ISR_install_vector( |
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[632e4306] | 447 | uint32_t vector, |
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| 448 | proc_ptr new_handler, |
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| 449 | proc_ptr *old_handler |
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[08330bf] | 450 | ); |
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| 451 | |
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[43e0599] | 452 | /** |
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[66fffc7] | 453 | * @brief CPU switch context. |
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[43e0599] | 454 | */ |
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[632e4306] | 455 | void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); |
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[08330bf] | 456 | |
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[db0df7b] | 457 | void _CPU_Context_restore( Context_Control *new_context ) |
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[c5ed148] | 458 | RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
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| 459 | |
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| 460 | #if defined(ARM_MULTILIB_ARCH_V7M) |
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[514705d] | 461 | void _ARMV7M_Start_multitasking( Context_Control *heir ); |
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[c5ed148] | 462 | #define _CPU_Start_multitasking _ARMV7M_Start_multitasking |
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| 463 | #endif |
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[08330bf] | 464 | |
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[39993d6] | 465 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
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| 466 | |
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| 467 | void _CPU_Context_validate( uintptr_t pattern ); |
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| 468 | |
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[f2f211c5] | 469 | #ifdef RTEMS_SMP |
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[53e008b] | 470 | uint32_t _CPU_SMP_Initialize( void ); |
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| 471 | |
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| 472 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
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| 473 | |
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| 474 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
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[4627fcd] | 475 | |
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[47d60134] | 476 | static inline uint32_t _CPU_SMP_Get_current_processor( void ) |
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[39e51758] | 477 | { |
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| 478 | uint32_t mpidr; |
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| 479 | |
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| 480 | /* Use ARMv7 Multiprocessor Affinity Register (MPIDR) */ |
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[47d60134] | 481 | __asm__ volatile ( |
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[39e51758] | 482 | "mrc p15, 0, %[mpidr], c0, c0, 5\n" |
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| 483 | : [mpidr] "=&r" (mpidr) |
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| 484 | ); |
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| 485 | |
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| 486 | return mpidr & 0xffU; |
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| 487 | } |
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| 488 | |
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[ca63ae2] | 489 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
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| 490 | |
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[f2f211c5] | 491 | static inline void _ARM_Send_event( void ) |
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| 492 | { |
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| 493 | __asm__ volatile ( "sev" : : : "memory" ); |
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| 494 | } |
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| 495 | |
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| 496 | static inline void _ARM_Wait_for_event( void ) |
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| 497 | { |
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| 498 | __asm__ volatile ( "wfe" : : : "memory" ); |
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| 499 | } |
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| 500 | |
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[07f6e419] | 501 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
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[f2f211c5] | 502 | { |
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| 503 | _ARM_Data_synchronization_barrier(); |
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| 504 | _ARM_Send_event(); |
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| 505 | } |
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| 506 | |
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[f7740e97] | 507 | static inline void _CPU_SMP_Processor_event_receive( void ) |
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[f2f211c5] | 508 | { |
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| 509 | _ARM_Wait_for_event(); |
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| 510 | _ARM_Data_memory_barrier(); |
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| 511 | } |
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| 512 | #endif |
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| 513 | |
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| 514 | |
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[632e4306] | 515 | static inline uint32_t CPU_swap_u32( uint32_t value ) |
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[08330bf] | 516 | { |
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[c5ed148] | 517 | #if defined(__thumb2__) |
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| 518 | __asm__ volatile ( |
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| 519 | "rev %0, %0" |
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| 520 | : "=r" (value) |
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| 521 | : "0" (value) |
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| 522 | ); |
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| 523 | return value; |
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| 524 | #elif defined(__thumb__) |
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[1c62f169] | 525 | uint32_t byte1, byte2, byte3, byte4, swapped; |
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[632e4306] | 526 | |
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[1c62f169] | 527 | byte4 = (value >> 24) & 0xff; |
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| 528 | byte3 = (value >> 16) & 0xff; |
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| 529 | byte2 = (value >> 8) & 0xff; |
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[632e4306] | 530 | byte1 = value & 0xff; |
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| 531 | |
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[1c62f169] | 532 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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| 533 | return swapped; |
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| 534 | #else |
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[632e4306] | 535 | uint32_t tmp = value; /* make compiler warnings go away */ |
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[9f9371f] | 536 | __asm__ volatile ("EOR %1, %0, %0, ROR #16\n" |
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[632e4306] | 537 | "BIC %1, %1, #0xff0000\n" |
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| 538 | "MOV %0, %0, ROR #8\n" |
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| 539 | "EOR %0, %0, %1, LSR #8\n" |
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| 540 | : "=r" (value), "=r" (tmp) |
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[1c62f169] | 541 | : "0" (value), "1" (tmp)); |
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| 542 | return value; |
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| 543 | #endif |
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[08330bf] | 544 | } |
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| 545 | |
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[632e4306] | 546 | static inline uint16_t CPU_swap_u16( uint16_t value ) |
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[fa237002] | 547 | { |
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[c5ed148] | 548 | #if defined(__thumb2__) |
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| 549 | __asm__ volatile ( |
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| 550 | "rev16 %0, %0" |
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| 551 | : "=r" (value) |
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| 552 | : "0" (value) |
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| 553 | ); |
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| 554 | return value; |
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| 555 | #else |
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[632e4306] | 556 | return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU)); |
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[c5ed148] | 557 | #endif |
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[632e4306] | 558 | } |
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[b32fe793] | 559 | |
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[24bf11e] | 560 | typedef uint32_t CPU_Counter_ticks; |
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| 561 | |
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| 562 | CPU_Counter_ticks _CPU_Counter_read( void ); |
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| 563 | |
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| 564 | CPU_Counter_ticks _CPU_Counter_difference( |
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| 565 | CPU_Counter_ticks second, |
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| 566 | CPU_Counter_ticks first |
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| 567 | ); |
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| 568 | |
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[f4539aa] | 569 | #if CPU_PROVIDES_IDLE_THREAD_BODY == TRUE |
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| 570 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
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| 571 | #endif |
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| 572 | |
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[78623bce] | 573 | /** @} */ |
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[b32fe793] | 574 | |
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[78623bce] | 575 | /** |
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| 576 | * @addtogroup ScoreCPUARM |
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| 577 | */ |
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[b697bc6] | 578 | /**@{**/ |
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[632e4306] | 579 | |
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[0d8cde9] | 580 | #if defined(ARM_MULTILIB_ARCH_V4) |
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| 581 | |
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[78623bce] | 582 | typedef enum { |
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| 583 | ARM_EXCEPTION_RESET = 0, |
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| 584 | ARM_EXCEPTION_UNDEF = 1, |
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| 585 | ARM_EXCEPTION_SWI = 2, |
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| 586 | ARM_EXCEPTION_PREF_ABORT = 3, |
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| 587 | ARM_EXCEPTION_DATA_ABORT = 4, |
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| 588 | ARM_EXCEPTION_RESERVED = 5, |
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| 589 | ARM_EXCEPTION_IRQ = 6, |
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| 590 | ARM_EXCEPTION_FIQ = 7, |
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[8d687737] | 591 | MAX_EXCEPTIONS = 8, |
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| 592 | ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff |
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[78623bce] | 593 | } Arm_symbolic_exception_name; |
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| 594 | |
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[0d8cde9] | 595 | #endif /* defined(ARM_MULTILIB_ARCH_V4) */ |
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[78623bce] | 596 | |
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[cfd8d7a] | 597 | typedef struct { |
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| 598 | uint32_t register_fpexc; |
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| 599 | uint32_t register_fpscr; |
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| 600 | uint64_t register_d0; |
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| 601 | uint64_t register_d1; |
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| 602 | uint64_t register_d2; |
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| 603 | uint64_t register_d3; |
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| 604 | uint64_t register_d4; |
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| 605 | uint64_t register_d5; |
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| 606 | uint64_t register_d6; |
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| 607 | uint64_t register_d7; |
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| 608 | uint64_t register_d8; |
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| 609 | uint64_t register_d9; |
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| 610 | uint64_t register_d10; |
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| 611 | uint64_t register_d11; |
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| 612 | uint64_t register_d12; |
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| 613 | uint64_t register_d13; |
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| 614 | uint64_t register_d14; |
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| 615 | uint64_t register_d15; |
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| 616 | uint64_t register_d16; |
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| 617 | uint64_t register_d17; |
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| 618 | uint64_t register_d18; |
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| 619 | uint64_t register_d19; |
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| 620 | uint64_t register_d20; |
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| 621 | uint64_t register_d21; |
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| 622 | uint64_t register_d22; |
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| 623 | uint64_t register_d23; |
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| 624 | uint64_t register_d24; |
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| 625 | uint64_t register_d25; |
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| 626 | uint64_t register_d26; |
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| 627 | uint64_t register_d27; |
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| 628 | uint64_t register_d28; |
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| 629 | uint64_t register_d29; |
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| 630 | uint64_t register_d30; |
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| 631 | uint64_t register_d31; |
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| 632 | } ARM_VFP_context; |
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| 633 | |
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[78623bce] | 634 | typedef struct { |
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| 635 | uint32_t register_r0; |
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| 636 | uint32_t register_r1; |
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| 637 | uint32_t register_r2; |
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| 638 | uint32_t register_r3; |
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[8d687737] | 639 | uint32_t register_r4; |
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| 640 | uint32_t register_r5; |
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| 641 | uint32_t register_r6; |
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| 642 | uint32_t register_r7; |
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| 643 | uint32_t register_r8; |
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| 644 | uint32_t register_r9; |
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| 645 | uint32_t register_r10; |
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| 646 | uint32_t register_r11; |
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| 647 | uint32_t register_r12; |
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| 648 | uint32_t register_sp; |
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[0d8cde9] | 649 | void *register_lr; |
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| 650 | void *register_pc; |
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| 651 | #if defined(ARM_MULTILIB_ARCH_V4) |
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[8d687737] | 652 | uint32_t register_cpsr; |
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| 653 | Arm_symbolic_exception_name vector; |
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[0d8cde9] | 654 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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| 655 | uint32_t register_xpsr; |
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| 656 | uint32_t vector; |
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| 657 | #endif |
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[cfd8d7a] | 658 | const ARM_VFP_context *vfp_context; |
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[78623bce] | 659 | } CPU_Exception_frame; |
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| 660 | |
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| 661 | typedef CPU_Exception_frame CPU_Interrupt_frame; |
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| 662 | |
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[815994f] | 663 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
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| 664 | |
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[50f3c42b] | 665 | void _ARM_Exception_default( CPU_Exception_frame *frame ); |
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| 666 | |
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[0d8cde9] | 667 | /** @} */ |
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| 668 | |
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[08330bf] | 669 | #ifdef __cplusplus |
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| 670 | } |
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| 671 | #endif |
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| 672 | |
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[632e4306] | 673 | #endif /* ASM */ |
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| 674 | |
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| 675 | #endif /* _RTEMS_SCORE_CPU_H */ |
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