1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief ARMV7M Architecture Support |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2011 Sebastian Huber. All rights reserved. |
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9 | * |
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10 | * embedded brains GmbH |
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11 | * Obere Lagerstr. 30 |
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12 | * 82178 Puchheim |
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13 | * Germany |
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14 | * <rtems@embedded-brains.de> |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.org/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #ifndef RTEMS_SCORE_ARMV7M_H |
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22 | #define RTEMS_SCORE_ARMV7M_H |
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23 | |
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24 | #include <rtems/score/cpu.h> |
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25 | |
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26 | #ifdef __cplusplus |
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27 | extern "C" { |
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28 | #endif /* __cplusplus */ |
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29 | |
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30 | #ifdef ARM_MULTILIB_ARCH_V7M |
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31 | |
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32 | typedef struct { |
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33 | uint32_t reserved_0; |
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34 | uint32_t ictr; |
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35 | uint32_t actlr; |
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36 | uint32_t reserved_1; |
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37 | } ARMV7M_ICTAC; |
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38 | |
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39 | typedef void (*ARMV7M_Exception_handler)(void); |
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40 | |
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41 | typedef struct { |
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42 | uint32_t register_r0; |
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43 | uint32_t register_r1; |
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44 | uint32_t register_r2; |
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45 | uint32_t register_r3; |
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46 | uint32_t register_r12; |
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47 | void *register_lr; |
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48 | void *register_pc; |
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49 | uint32_t register_xpsr; |
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50 | } ARMV7M_Exception_frame; |
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51 | |
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52 | typedef struct { |
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53 | uint32_t cpuid; |
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54 | |
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55 | #define ARMV7M_SCB_ICSR_NMIPENDSET (1U << 31) |
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56 | #define ARMV7M_SCB_ICSR_PENDSVSET (1U << 28) |
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57 | #define ARMV7M_SCB_ICSR_PENDSVCLR (1U << 27) |
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58 | #define ARMV7M_SCB_ICSR_PENDSTSET (1U << 26) |
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59 | #define ARMV7M_SCB_ICSR_PENDSTCLR (1U << 25) |
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60 | #define ARMV7M_SCB_ICSR_ISRPREEMPT (1U << 23) |
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61 | #define ARMV7M_SCB_ICSR_ISRPENDING (1U << 22) |
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62 | #define ARMV7M_SCB_ICSR_VECTPENDING_GET(reg) (((reg) >> 12) & 0x1ffU) |
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63 | #define ARMV7M_SCB_ICSR_RETTOBASE (1U << 11) |
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64 | #define ARMV7M_SCB_ICSR_VECTACTIVE_GET(reg) ((reg) & 0x1ffU) |
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65 | uint32_t icsr; |
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66 | |
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67 | ARMV7M_Exception_handler *vtor; |
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68 | |
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69 | #define ARMV7M_SCB_AIRCR_VECTKEY (0x05fa << 16) |
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70 | #define ARMV7M_SCB_AIRCR_ENDIANESS (1U << 15) |
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71 | #define ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT 8 |
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72 | #define ARMV7M_SCB_AIRCR_PRIGROUP_MASK \ |
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73 | ((0x7U) << ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT) |
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74 | #define ARMV7M_SCB_AIRCR_PRIGROUP(val) \ |
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75 | (((val) << ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT) & ARMV7M_SCB_AIRCR_PRIGROUP_MASK) |
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76 | #define ARMV7M_SCB_AIRCR_PRIGROUP_GET(reg) \ |
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77 | (((val) & ARMV7M_SCB_AIRCR_PRIGROUP_MASK) >> ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT) |
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78 | #define ARMV7M_SCB_AIRCR_PRIGROUP_SET(reg, val) \ |
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79 | (((reg) & ~ARMV7M_SCB_AIRCR_PRIGROUP_MASK) | ARMV7M_SCB_AIRCR_PRIGROUP(val)) |
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80 | #define ARMV7M_SCB_AIRCR_SYSRESETREQ (1U << 2) |
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81 | #define ARMV7M_SCB_AIRCR_VECTCLRACTIVE (1U << 1) |
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82 | #define ARMV7M_SCB_AIRCR_VECTRESET (1U << 0) |
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83 | uint32_t aircr; |
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84 | |
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85 | uint32_t scr; |
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86 | uint32_t ccr; |
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87 | uint8_t shpr [12]; |
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88 | |
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89 | #define ARMV7M_SCB_SHCSR_USGFAULTENA (1U << 18) |
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90 | #define ARMV7M_SCB_SHCSR_BUSFAULTENA (1U << 17) |
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91 | #define ARMV7M_SCB_SHCSR_MEMFAULTENA (1U << 16) |
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92 | uint32_t shcsr; |
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93 | |
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94 | uint32_t cfsr; |
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95 | uint32_t hfsr; |
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96 | uint32_t dfsr; |
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97 | uint32_t mmfar; |
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98 | uint32_t bfar; |
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99 | uint32_t afsr; |
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100 | } ARMV7M_SCB; |
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101 | |
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102 | typedef struct { |
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103 | #define ARMV7M_SYSTICK_CSR_COUNTFLAG (1U << 16) |
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104 | #define ARMV7M_SYSTICK_CSR_CLKSOURCE (1U << 2) |
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105 | #define ARMV7M_SYSTICK_CSR_TICKINT (1U << 1) |
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106 | #define ARMV7M_SYSTICK_CSR_ENABLE (1U << 0) |
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107 | uint32_t csr; |
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108 | |
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109 | uint32_t rvr; |
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110 | uint32_t cvr; |
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111 | |
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112 | #define ARMV7M_SYSTICK_CALIB_NOREF (1U << 31) |
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113 | #define ARMV7M_SYSTICK_CALIB_SKEW (1U << 30) |
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114 | #define ARMV7M_SYSTICK_CALIB_TENMS_GET(reg) ((reg) & 0xffffffU) |
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115 | uint32_t calib; |
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116 | } ARMV7M_Systick; |
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117 | |
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118 | typedef struct { |
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119 | uint32_t iser [8]; |
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120 | uint32_t reserved_0 [24]; |
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121 | uint32_t icer [8]; |
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122 | uint32_t reserved_1 [24]; |
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123 | uint32_t ispr [8]; |
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124 | uint32_t reserved_2 [24]; |
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125 | uint32_t icpr [8]; |
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126 | uint32_t reserved_3 [24]; |
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127 | uint32_t iabr [8]; |
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128 | uint32_t reserved_4 [56]; |
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129 | uint8_t ipr [240]; |
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130 | uint32_t reserved_5 [644]; |
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131 | uint32_t stir; |
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132 | } ARMV7M_NVIC; |
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133 | |
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134 | typedef struct { |
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135 | #define ARMV7M_MPU_TYPE_IREGION_GET(reg) (((reg) >> 16) & 0xffU) |
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136 | #define ARMV7M_MPU_TYPE_DREGION_GET(reg) (((reg) >> 8) & 0xffU) |
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137 | #define ARMV7M_MPU_TYPE_SEPARATE (1U << 0) |
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138 | uint32_t type; |
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139 | |
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140 | #define ARMV7M_MPU_CTRL_PRIVDEFENA (1U << 2) |
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141 | #define ARMV7M_MPU_CTRL_HFNMIENA (1U << 1) |
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142 | #define ARMV7M_MPU_CTRL_ENABLE (1U << 0) |
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143 | uint32_t ctrl; |
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144 | |
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145 | uint32_t rnr; |
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146 | |
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147 | #define ARMV7M_MPU_RBAR_ADDR_SHIFT 5 |
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148 | #define ARMV7M_MPU_RBAR_ADDR_MASK \ |
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149 | ((0x7ffffffU) << ARMV7M_MPU_RBAR_ADDR_SHIFT) |
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150 | #define ARMV7M_MPU_RBAR_ADDR(val) \ |
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151 | (((val) << ARMV7M_MPU_RBAR_ADDR_SHIFT) & ARMV7M_MPU_RBAR_ADDR_MASK) |
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152 | #define ARMV7M_MPU_RBAR_ADDR_GET(reg) \ |
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153 | (((val) & ARMV7M_MPU_RBAR_ADDR_MASK) >> ARMV7M_MPU_RBAR_ADDR_SHIFT) |
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154 | #define ARMV7M_MPU_RBAR_ADDR_SET(reg, val) \ |
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155 | (((reg) & ~ARMV7M_MPU_RBAR_ADDR_MASK) | ARMV7M_MPU_RBAR_ADDR(val)) |
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156 | #define ARMV7M_MPU_RBAR_VALID (1U << 4) |
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157 | #define ARMV7M_MPU_RBAR_REGION_SHIFT 0 |
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158 | #define ARMV7M_MPU_RBAR_REGION_MASK \ |
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159 | ((0xfU) << ARMV7M_MPU_RBAR_REGION_SHIFT) |
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160 | #define ARMV7M_MPU_RBAR_REGION(val) \ |
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161 | (((val) << ARMV7M_MPU_RBAR_REGION_SHIFT) & ARMV7M_MPU_RBAR_REGION_MASK) |
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162 | #define ARMV7M_MPU_RBAR_REGION_GET(reg) \ |
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163 | (((val) & ARMV7M_MPU_RBAR_REGION_MASK) >> ARMV7M_MPU_RBAR_REGION_SHIFT) |
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164 | #define ARMV7M_MPU_RBAR_REGION_SET(reg, val) \ |
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165 | (((reg) & ~ARMV7M_MPU_RBAR_REGION_MASK) | ARMV7M_MPU_RBAR_REGION(val)) |
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166 | uint32_t rbar; |
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167 | |
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168 | #define ARMV7M_MPU_RASR_XN (1U << 28) |
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169 | #define ARMV7M_MPU_RASR_AP_SHIFT 24 |
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170 | #define ARMV7M_MPU_RASR_AP_MASK \ |
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171 | ((0x7U) << ARMV7M_MPU_RASR_AP_SHIFT) |
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172 | #define ARMV7M_MPU_RASR_AP(val) \ |
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173 | (((val) << ARMV7M_MPU_RASR_AP_SHIFT) & ARMV7M_MPU_RASR_AP_MASK) |
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174 | #define ARMV7M_MPU_RASR_AP_GET(reg) \ |
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175 | (((val) & ARMV7M_MPU_RASR_AP_MASK) >> ARMV7M_MPU_RASR_AP_SHIFT) |
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176 | #define ARMV7M_MPU_RASR_AP_SET(reg, val) \ |
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177 | (((reg) & ~ARMV7M_MPU_RASR_AP_MASK) | ARMV7M_MPU_RASR_AP(val)) |
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178 | #define ARMV7M_MPU_RASR_TEX_SHIFT 19 |
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179 | #define ARMV7M_MPU_RASR_TEX_MASK \ |
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180 | ((0x7U) << ARMV7M_MPU_RASR_TEX_SHIFT) |
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181 | #define ARMV7M_MPU_RASR_TEX(val) \ |
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182 | (((val) << ARMV7M_MPU_RASR_TEX_SHIFT) & ARMV7M_MPU_RASR_TEX_MASK) |
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183 | #define ARMV7M_MPU_RASR_TEX_GET(reg) \ |
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184 | (((val) & ARMV7M_MPU_RASR_TEX_MASK) >> ARMV7M_MPU_RASR_TEX_SHIFT) |
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185 | #define ARMV7M_MPU_RASR_TEX_SET(reg, val) \ |
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186 | (((reg) & ~ARMV7M_MPU_RASR_TEX_MASK) | ARMV7M_MPU_RASR_TEX(val)) |
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187 | #define ARMV7M_MPU_RASR_S (1U << 18) |
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188 | #define ARMV7M_MPU_RASR_C (1U << 17) |
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189 | #define ARMV7M_MPU_RASR_B (1U << 16) |
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190 | #define ARMV7M_MPU_RASR_SRD_SHIFT 8 |
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191 | #define ARMV7M_MPU_RASR_SRD_MASK \ |
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192 | ((0xffU) << ARMV7M_MPU_RASR_SRD_SHIFT) |
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193 | #define ARMV7M_MPU_RASR_SRD(val) \ |
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194 | (((val) << ARMV7M_MPU_RASR_SRD_SHIFT) & ARMV7M_MPU_RASR_SRD_MASK) |
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195 | #define ARMV7M_MPU_RASR_SRD_GET(reg) \ |
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196 | (((val) & ARMV7M_MPU_RASR_SRD_MASK) >> ARMV7M_MPU_RASR_SRD_SHIFT) |
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197 | #define ARMV7M_MPU_RASR_SRD_SET(reg, val) \ |
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198 | (((reg) & ~ARMV7M_MPU_RASR_SRD_MASK) | ARMV7M_MPU_RASR_SRD(val)) |
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199 | #define ARMV7M_MPU_RASR_SIZE_SHIFT 1 |
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200 | #define ARMV7M_MPU_RASR_SIZE_MASK \ |
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201 | ((0x1fU) << ARMV7M_MPU_RASR_SIZE_SHIFT) |
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202 | #define ARMV7M_MPU_RASR_SIZE(val) \ |
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203 | (((val) << ARMV7M_MPU_RASR_SIZE_SHIFT) & ARMV7M_MPU_RASR_SIZE_MASK) |
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204 | #define ARMV7M_MPU_RASR_SIZE_GET(reg) \ |
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205 | (((val) & ARMV7M_MPU_RASR_SIZE_MASK) >> ARMV7M_MPU_RASR_SIZE_SHIFT) |
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206 | #define ARMV7M_MPU_RASR_SIZE_SET(reg, val) \ |
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207 | (((reg) & ~ARMV7M_MPU_RASR_SIZE_MASK) | ARMV7M_MPU_RASR_SIZE(val)) |
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208 | #define ARMV7M_MPU_RASR_ENABLE (1U << 0) |
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209 | uint32_t rasr; |
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210 | |
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211 | uint32_t rbar_a1; |
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212 | uint32_t rasr_a1; |
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213 | uint32_t rbar_a2; |
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214 | uint32_t rasr_a2; |
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215 | uint32_t rbar_a3; |
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216 | uint32_t rasr_a3; |
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217 | } ARMV7M_MPU; |
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218 | |
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219 | typedef enum { |
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220 | ARMV7M_MPU_AP_PRIV_NO_USER_NO, |
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221 | ARMV7M_MPU_AP_PRIV_RW_USER_NO, |
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222 | ARMV7M_MPU_AP_PRIV_RW_USER_RO, |
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223 | ARMV7M_MPU_AP_PRIV_RW_USER_RW, |
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224 | ARMV7M_MPU_AP_PRIV_RO_USER_NO = 0x5, |
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225 | ARMV7M_MPU_AP_PRIV_RO_USER_RO, |
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226 | } ARMV7M_MPU_Access_permissions; |
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227 | |
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228 | typedef enum { |
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229 | ARMV7M_MPU_ATTR_R = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RO_USER_NO) |
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230 | | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_XN, |
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231 | ARMV7M_MPU_ATTR_RW = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO) |
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232 | | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_XN | ARMV7M_MPU_RASR_B, |
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233 | ARMV7M_MPU_ATTR_RWX = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO) |
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234 | | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B, |
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235 | ARMV7M_MPU_ATTR_X = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_NO_USER_NO) |
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236 | | ARMV7M_MPU_RASR_C, |
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237 | ARMV7M_MPU_ATTR_RX = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RO_USER_NO) |
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238 | | ARMV7M_MPU_RASR_C, |
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239 | ARMV7M_MPU_ATTR_IO = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO) |
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240 | | ARMV7M_MPU_RASR_XN, |
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241 | } ARMV7M_MPU_Attributes; |
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242 | |
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243 | typedef enum { |
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244 | ARMV7M_MPU_SIZE_32_B = 0x4, |
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245 | ARMV7M_MPU_SIZE_64_B, |
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246 | ARMV7M_MPU_SIZE_128_B, |
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247 | ARMV7M_MPU_SIZE_256_B, |
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248 | ARMV7M_MPU_SIZE_512_B, |
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249 | ARMV7M_MPU_SIZE_1_KB, |
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250 | ARMV7M_MPU_SIZE_2_KB, |
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251 | ARMV7M_MPU_SIZE_4_KB, |
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252 | ARMV7M_MPU_SIZE_8_KB, |
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253 | ARMV7M_MPU_SIZE_16_KB, |
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254 | ARMV7M_MPU_SIZE_32_KB, |
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255 | ARMV7M_MPU_SIZE_64_KB, |
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256 | ARMV7M_MPU_SIZE_128_KB, |
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257 | ARMV7M_MPU_SIZE_256_KB, |
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258 | ARMV7M_MPU_SIZE_512_KB, |
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259 | ARMV7M_MPU_SIZE_1_MB, |
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260 | ARMV7M_MPU_SIZE_2_MB, |
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261 | ARMV7M_MPU_SIZE_4_MB, |
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262 | ARMV7M_MPU_SIZE_8_MB, |
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263 | ARMV7M_MPU_SIZE_16_MB, |
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264 | ARMV7M_MPU_SIZE_32_MB, |
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265 | ARMV7M_MPU_SIZE_64_MB, |
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266 | ARMV7M_MPU_SIZE_128_MB, |
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267 | ARMV7M_MPU_SIZE_256_MB, |
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268 | ARMV7M_MPU_SIZE_512_MB, |
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269 | ARMV7M_MPU_SIZE_1_GB, |
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270 | ARMV7M_MPU_SIZE_2_GB, |
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271 | ARMV7M_MPU_SIZE_4_GB |
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272 | } ARMV7M_MPU_Size; |
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273 | |
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274 | typedef struct { |
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275 | uint32_t rbar; |
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276 | uint32_t rasr; |
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277 | } ARMV7M_MPU_Region; |
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278 | |
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279 | #define ARMV7M_MPU_REGION_INITIALIZER(idx, addr, size, attr) \ |
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280 | { \ |
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281 | ((addr) & ARMV7M_MPU_RBAR_ADDR_MASK) \ |
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282 | | ARMV7M_MPU_RBAR_VALID \ |
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283 | | ARMV7M_MPU_RBAR_REGION(idx), \ |
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284 | ARMV7M_MPU_RASR_SIZE(size) | (attr) | ARMV7M_MPU_RASR_ENABLE \ |
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285 | } |
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286 | |
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287 | #define ARMV7M_MPU_REGION_DISABLED_INITIALIZER(idx) \ |
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288 | { \ |
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289 | ARMV7M_MPU_RBAR_VALID | ARMV7M_MPU_RBAR_REGION(idx), \ |
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290 | 0 \ |
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291 | } |
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292 | |
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293 | #define ARMV7M_SCS_BASE 0xe000e000 |
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294 | #define ARMV7M_ICTAC_BASE (ARMV7M_SCS_BASE + 0x0) |
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295 | #define ARMV7M_SYSTICK_BASE (ARMV7M_SCS_BASE + 0x10) |
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296 | #define ARMV7M_NVIC_BASE (ARMV7M_SCS_BASE + 0x100) |
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297 | #define ARMV7M_SCB_BASE (ARMV7M_SCS_BASE + 0xd00) |
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298 | #define ARMV7M_MPU_BASE (ARMV7M_SCS_BASE + 0xd90) |
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299 | |
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300 | #define _ARMV7M_ICTAC \ |
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301 | ((volatile ARMV7M_ICTAC *) ARMV7M_ICTAC_BASE) |
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302 | #define _ARMV7M_SCB \ |
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303 | ((volatile ARMV7M_SCB *) ARMV7M_SCB_BASE) |
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304 | #define _ARMV7M_Systick \ |
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305 | ((volatile ARMV7M_Systick *) ARMV7M_SYSTICK_BASE) |
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306 | #define _ARMV7M_NVIC \ |
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307 | ((volatile ARMV7M_NVIC *) ARMV7M_NVIC_BASE) |
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308 | #define _ARMV7M_MPU \ |
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309 | ((volatile ARMV7M_MPU *) ARMV7M_MPU_BASE) |
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310 | |
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311 | #define ARMV7M_VECTOR_MSP 0 |
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312 | #define ARMV7M_VECTOR_RESET 1 |
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313 | #define ARMV7M_VECTOR_NMI 2 |
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314 | #define ARMV7M_VECTOR_HARD_FAULT 3 |
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315 | #define ARMV7M_VECTOR_MEM_MANAGE 4 |
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316 | #define ARMV7M_VECTOR_BUS_FAULT 5 |
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317 | #define ARMV7M_VECTOR_USAGE_FAULT 6 |
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318 | #define ARMV7M_VECTOR_SVC 11 |
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319 | #define ARMV7M_VECTOR_DEBUG_MONITOR 12 |
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320 | #define ARMV7M_VECTOR_PENDSV 14 |
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321 | #define ARMV7M_VECTOR_SYSTICK 15 |
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322 | #define ARMV7M_VECTOR_IRQ(n) ((n) + 16) |
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323 | #define ARMV7M_IRQ_OF_VECTOR(n) ((n) - 16) |
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324 | |
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325 | #define ARMV7M_EXCEPTION_PRIORITY_LOWEST 255 |
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326 | |
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327 | static inline bool _ARMV7M_Is_vector_an_irq( int vector ) |
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328 | { |
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329 | return vector >= 16; |
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330 | } |
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331 | |
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332 | static inline uint32_t _ARMV7M_Get_basepri(void) |
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333 | { |
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334 | uint32_t val; |
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335 | __asm__ volatile ("mrs %[val], basepri\n" : [val] "=&r" (val)); |
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336 | return val; |
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337 | } |
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338 | |
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339 | static inline void _ARMV7M_Set_basepri(uint32_t val) |
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340 | { |
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341 | __asm__ volatile ("msr basepri, %[val]\n" : : [val] "r" (val)); |
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342 | } |
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343 | |
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344 | static inline uint32_t _ARMV7M_Get_primask(void) |
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345 | { |
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346 | uint32_t val; |
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347 | __asm__ volatile ("mrs %[val], primask\n" : [val] "=&r" (val)); |
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348 | return val; |
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349 | } |
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350 | |
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351 | static inline void _ARMV7M_Set_primask(uint32_t val) |
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352 | { |
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353 | __asm__ volatile ("msr primask, %[val]\n" : : [val] "r" (val)); |
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354 | } |
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355 | |
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356 | static inline uint32_t _ARMV7M_Get_faultmask(void) |
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357 | { |
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358 | uint32_t val; |
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359 | __asm__ volatile ("mrs %[val], faultmask\n" : [val] "=&r" (val)); |
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360 | return val; |
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361 | } |
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362 | |
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363 | static inline void _ARMV7M_Set_faultmask(uint32_t val) |
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364 | { |
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365 | __asm__ volatile ("msr faultmask, %[val]\n" : : [val] "r" (val)); |
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366 | } |
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367 | |
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368 | static inline uint32_t _ARMV7M_Get_control(void) |
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369 | { |
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370 | uint32_t val; |
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371 | __asm__ volatile ("mrs %[val], control\n" : [val] "=&r" (val)); |
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372 | return val; |
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373 | } |
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374 | |
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375 | static inline void _ARMV7M_Set_control(uint32_t val) |
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376 | { |
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377 | __asm__ volatile ("msr control, %[val]\n" : : [val] "r" (val)); |
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378 | } |
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379 | |
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380 | static inline uint32_t _ARMV7M_Get_MSP(void) |
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381 | { |
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382 | uint32_t val; |
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383 | __asm__ volatile ("mrs %[val], msp\n" : [val] "=&r" (val)); |
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384 | return val; |
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385 | } |
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386 | |
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387 | static inline void _ARMV7M_Set_MSP(uint32_t val) |
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388 | { |
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389 | __asm__ volatile ("msr msp, %[val]\n" : : [val] "r" (val)); |
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390 | } |
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391 | |
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392 | static inline uint32_t _ARMV7M_Get_PSP(void) |
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393 | { |
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394 | uint32_t val; |
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395 | __asm__ volatile ("mrs %[val], psp\n" : [val] "=&r" (val)); |
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396 | return val; |
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397 | } |
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398 | |
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399 | static inline void _ARMV7M_Set_PSP(uint32_t val) |
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400 | { |
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401 | __asm__ volatile ("msr psp, %[val]\n" : : [val] "r" (val)); |
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402 | } |
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403 | |
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404 | static inline uint32_t _ARMV7M_Get_XPSR(void) |
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405 | { |
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406 | uint32_t val; |
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407 | __asm__ volatile ("mrs %[val], xpsr\n" : [val] "=&r" (val)); |
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408 | return val; |
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409 | } |
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410 | |
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411 | static inline bool _ARMV7M_NVIC_Is_enabled( int irq ) |
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412 | { |
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413 | int index = irq >> 5; |
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414 | uint32_t bit = 1U << (irq & 0x1f); |
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415 | |
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416 | return (_ARMV7M_NVIC->iser [index] & bit) != 0; |
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417 | } |
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418 | |
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419 | static inline void _ARMV7M_NVIC_Set_enable( int irq ) |
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420 | { |
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421 | int index = irq >> 5; |
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422 | uint32_t bit = 1U << (irq & 0x1f); |
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423 | |
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424 | _ARMV7M_NVIC->iser [index] = bit; |
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425 | } |
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426 | |
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427 | static inline void _ARMV7M_NVIC_Clear_enable( int irq ) |
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428 | { |
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429 | int index = irq >> 5; |
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430 | uint32_t bit = 1U << (irq & 0x1f); |
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431 | |
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432 | _ARMV7M_NVIC->icer [index] = bit; |
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433 | } |
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434 | |
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435 | static inline bool _ARMV7M_NVIC_Is_pending( int irq ) |
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436 | { |
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437 | int index = irq >> 5; |
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438 | uint32_t bit = 1U << (irq & 0x1f); |
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439 | |
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440 | return (_ARMV7M_NVIC->ispr [index] & bit) != 0; |
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441 | } |
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442 | |
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443 | static inline void _ARMV7M_NVIC_Set_pending( int irq ) |
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444 | { |
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445 | int index = irq >> 5; |
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446 | uint32_t bit = 1U << (irq & 0x1f); |
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447 | |
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448 | _ARMV7M_NVIC->ispr [index] = bit; |
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449 | } |
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450 | |
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451 | static inline void _ARMV7M_NVIC_Clear_pending( int irq ) |
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452 | { |
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453 | int index = irq >> 5; |
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454 | uint32_t bit = 1U << (irq & 0x1f); |
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455 | |
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456 | _ARMV7M_NVIC->icpr [index] = bit; |
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457 | } |
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458 | |
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459 | static inline bool _ARMV7M_NVIC_Is_active( int irq ) |
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460 | { |
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461 | int index = irq >> 5; |
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462 | uint32_t bit = 1U << (irq & 0x1f); |
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463 | |
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464 | return (_ARMV7M_NVIC->iabr [index] & bit) != 0; |
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465 | } |
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466 | |
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467 | static inline void _ARMV7M_NVIC_Set_priority( int irq, int priority ) |
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468 | { |
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469 | _ARMV7M_NVIC->ipr [irq] = (uint8_t) priority; |
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470 | } |
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471 | |
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472 | static inline int _ARMV7M_NVIC_Get_priority( int irq ) |
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473 | { |
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474 | return _ARMV7M_NVIC->ipr [irq]; |
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475 | } |
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476 | |
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477 | int _ARMV7M_Get_exception_priority( int vector ); |
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478 | |
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479 | void _ARMV7M_Set_exception_priority( int vector, int priority ); |
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480 | |
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481 | ARMV7M_Exception_handler _ARMV7M_Get_exception_handler( int index ); |
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482 | |
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483 | void _ARMV7M_Set_exception_handler( |
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484 | int index, |
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485 | ARMV7M_Exception_handler handler |
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486 | ); |
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487 | |
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488 | /** |
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489 | * @brief ARMV7M set exception priority and handler. |
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490 | */ |
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491 | void _ARMV7M_Set_exception_priority_and_handler( |
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492 | int index, |
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493 | int priority, |
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494 | ARMV7M_Exception_handler handler |
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495 | ); |
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496 | |
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497 | void _ARMV7M_Exception_default( void ); |
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498 | |
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499 | void _ARMV7M_Interrupt_service_enter( void ); |
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500 | |
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501 | void _ARMV7M_Interrupt_service_leave( void ); |
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502 | |
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503 | void _ARMV7M_Pendable_service_call( void ); |
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504 | |
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505 | void _ARMV7M_Supervisor_call( void ); |
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506 | |
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507 | #endif /* ARM_MULTILIB_ARCH_V7M */ |
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508 | |
---|
509 | #ifdef __cplusplus |
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510 | } |
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511 | #endif /* __cplusplus */ |
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512 | |
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513 | #endif /* RTEMS_SCORE_ARMV7M_H */ |
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