source: rtems/cpukit/score/cpu/arm/rtems/score/armv7m.h @ 8ae37323

4.115
Last change on this file since 8ae37323 was 8ae37323, checked in by Sebastian Huber <sebastian.huber@…>, on 08/10/14 at 16:36:30

arm: Add support for FPv4-SP floating point unit

This floating point unit is available in Cortex-M4 processors and
defined by ARMv7-M. This adds basic support for other VFP-D16 variants.

  • Property mode set to 100644
File size: 14.6 KB
Line 
1/**
2 * @file
3 *
4 * @brief ARMV7M Architecture Support
5 */
6
7/*
8 * Copyright (c) 2011-2014 Sebastian Huber.  All rights reserved.
9 *
10 *  embedded brains GmbH
11 *  Obere Lagerstr. 30
12 *  82178 Puchheim
13 *  Germany
14 *  <rtems@embedded-brains.de>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 */
20
21#ifndef RTEMS_SCORE_ARMV7M_H
22#define RTEMS_SCORE_ARMV7M_H
23
24#include <rtems/score/cpu.h>
25
26#ifdef __cplusplus
27extern "C" {
28#endif /* __cplusplus */
29
30#ifdef ARM_MULTILIB_ARCH_V7M
31
32/* Coprocessor Access Control Register, CPACR */
33#define ARMV7M_CPACR 0xe000ed88
34
35#ifndef ASM
36
37typedef struct {
38  uint32_t reserved_0;
39  uint32_t ictr;
40  uint32_t actlr;
41  uint32_t reserved_1;
42} ARMV7M_ICTAC;
43
44typedef void (*ARMV7M_Exception_handler)(void);
45
46typedef struct {
47  uint32_t register_r0;
48  uint32_t register_r1;
49  uint32_t register_r2;
50  uint32_t register_r3;
51  uint32_t register_r12;
52  void *register_lr;
53  void *register_pc;
54  uint32_t register_xpsr;
55#ifdef ARM_MULTILIB_VFP
56  uint32_t register_s0;
57  uint32_t register_s1;
58  uint32_t register_s2;
59  uint32_t register_s3;
60  uint32_t register_s4;
61  uint32_t register_s5;
62  uint32_t register_s6;
63  uint32_t register_s7;
64  uint32_t register_s8;
65  uint32_t register_s9;
66  uint32_t register_s10;
67  uint32_t register_s11;
68  uint32_t register_s12;
69  uint32_t register_s13;
70  uint32_t register_s14;
71  uint32_t register_s15;
72  uint32_t register_fpscr;
73  uint32_t reserved;
74#endif
75} ARMV7M_Exception_frame;
76
77typedef struct {
78  uint32_t cpuid;
79
80#define ARMV7M_SCB_ICSR_NMIPENDSET (1U << 31)
81#define ARMV7M_SCB_ICSR_PENDSVSET (1U << 28)
82#define ARMV7M_SCB_ICSR_PENDSVCLR (1U << 27)
83#define ARMV7M_SCB_ICSR_PENDSTSET (1U << 26)
84#define ARMV7M_SCB_ICSR_PENDSTCLR (1U << 25)
85#define ARMV7M_SCB_ICSR_ISRPREEMPT (1U << 23)
86#define ARMV7M_SCB_ICSR_ISRPENDING (1U << 22)
87#define ARMV7M_SCB_ICSR_VECTPENDING_GET(reg) (((reg) >> 12) & 0x1ffU)
88#define ARMV7M_SCB_ICSR_RETTOBASE (1U << 11)
89#define ARMV7M_SCB_ICSR_VECTACTIVE_GET(reg) ((reg) & 0x1ffU)
90  uint32_t icsr;
91
92  ARMV7M_Exception_handler *vtor;
93
94#define ARMV7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
95#define ARMV7M_SCB_AIRCR_ENDIANESS (1U << 15)
96#define ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT 8
97#define ARMV7M_SCB_AIRCR_PRIGROUP_MASK \
98  ((0x7U) << ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT)
99#define ARMV7M_SCB_AIRCR_PRIGROUP(val) \
100  (((val) << ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT) & ARMV7M_SCB_AIRCR_PRIGROUP_MASK)
101#define ARMV7M_SCB_AIRCR_PRIGROUP_GET(reg) \
102  (((val) & ARMV7M_SCB_AIRCR_PRIGROUP_MASK) >> ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT)
103#define ARMV7M_SCB_AIRCR_PRIGROUP_SET(reg, val) \
104  (((reg) & ~ARMV7M_SCB_AIRCR_PRIGROUP_MASK) | ARMV7M_SCB_AIRCR_PRIGROUP(val))
105#define ARMV7M_SCB_AIRCR_SYSRESETREQ (1U << 2)
106#define ARMV7M_SCB_AIRCR_VECTCLRACTIVE (1U << 1)
107#define ARMV7M_SCB_AIRCR_VECTRESET (1U << 0)
108  uint32_t aircr;
109
110  uint32_t scr;
111  uint32_t ccr;
112  uint8_t shpr [12];
113
114#define ARMV7M_SCB_SHCSR_USGFAULTENA (1U << 18)
115#define ARMV7M_SCB_SHCSR_BUSFAULTENA (1U << 17)
116#define ARMV7M_SCB_SHCSR_MEMFAULTENA (1U << 16)
117  uint32_t shcsr;
118
119  uint32_t cfsr;
120  uint32_t hfsr;
121  uint32_t dfsr;
122  uint32_t mmfar;
123  uint32_t bfar;
124  uint32_t afsr;
125  uint32_t reserved_e000ed40[18];
126  uint32_t cpacr;
127  uint32_t reserved_e000ed8c[106];
128  uint32_t fpccr;
129  uint32_t fpcar;
130  uint32_t fpdscr;
131  uint32_t mvfr0;
132  uint32_t mvfr1;
133} ARMV7M_SCB;
134
135typedef struct {
136#define ARMV7M_SYSTICK_CSR_COUNTFLAG (1U << 16)
137#define ARMV7M_SYSTICK_CSR_CLKSOURCE (1U << 2)
138#define ARMV7M_SYSTICK_CSR_TICKINT (1U << 1)
139#define ARMV7M_SYSTICK_CSR_ENABLE (1U << 0)
140  uint32_t csr;
141
142  uint32_t rvr;
143  uint32_t cvr;
144
145#define ARMV7M_SYSTICK_CALIB_NOREF (1U << 31)
146#define ARMV7M_SYSTICK_CALIB_SKEW (1U << 30)
147#define ARMV7M_SYSTICK_CALIB_TENMS_GET(reg) ((reg) & 0xffffffU)
148  uint32_t calib;
149} ARMV7M_Systick;
150
151typedef struct {
152  uint32_t iser [8];
153  uint32_t reserved_0 [24];
154  uint32_t icer [8];
155  uint32_t reserved_1 [24];
156  uint32_t ispr [8];
157  uint32_t reserved_2 [24];
158  uint32_t icpr [8];
159  uint32_t reserved_3 [24];
160  uint32_t iabr [8];
161  uint32_t reserved_4 [56];
162  uint8_t  ipr [240];
163  uint32_t reserved_5 [644];
164  uint32_t stir;
165} ARMV7M_NVIC;
166
167typedef struct {
168#define ARMV7M_MPU_TYPE_IREGION_GET(reg) (((reg) >> 16) & 0xffU)
169#define ARMV7M_MPU_TYPE_DREGION_GET(reg) (((reg) >> 8) & 0xffU)
170#define ARMV7M_MPU_TYPE_SEPARATE (1U << 0)
171  uint32_t type;
172
173#define ARMV7M_MPU_CTRL_PRIVDEFENA (1U << 2)
174#define ARMV7M_MPU_CTRL_HFNMIENA (1U << 1)
175#define ARMV7M_MPU_CTRL_ENABLE (1U << 0)
176  uint32_t ctrl;
177
178  uint32_t rnr;
179
180#define ARMV7M_MPU_RBAR_ADDR_SHIFT 5
181#define ARMV7M_MPU_RBAR_ADDR_MASK \
182  ((0x7ffffffU) << ARMV7M_MPU_RBAR_ADDR_SHIFT)
183#define ARMV7M_MPU_RBAR_ADDR(val) \
184  (((val) << ARMV7M_MPU_RBAR_ADDR_SHIFT) & ARMV7M_MPU_RBAR_ADDR_MASK)
185#define ARMV7M_MPU_RBAR_ADDR_GET(reg) \
186  (((val) & ARMV7M_MPU_RBAR_ADDR_MASK) >> ARMV7M_MPU_RBAR_ADDR_SHIFT)
187#define ARMV7M_MPU_RBAR_ADDR_SET(reg, val) \
188  (((reg) & ~ARMV7M_MPU_RBAR_ADDR_MASK) | ARMV7M_MPU_RBAR_ADDR(val))
189#define ARMV7M_MPU_RBAR_VALID (1U << 4)
190#define ARMV7M_MPU_RBAR_REGION_SHIFT 0
191#define ARMV7M_MPU_RBAR_REGION_MASK \
192  ((0xfU) << ARMV7M_MPU_RBAR_REGION_SHIFT)
193#define ARMV7M_MPU_RBAR_REGION(val) \
194  (((val) << ARMV7M_MPU_RBAR_REGION_SHIFT) & ARMV7M_MPU_RBAR_REGION_MASK)
195#define ARMV7M_MPU_RBAR_REGION_GET(reg) \
196  (((val) & ARMV7M_MPU_RBAR_REGION_MASK) >> ARMV7M_MPU_RBAR_REGION_SHIFT)
197#define ARMV7M_MPU_RBAR_REGION_SET(reg, val) \
198  (((reg) & ~ARMV7M_MPU_RBAR_REGION_MASK) | ARMV7M_MPU_RBAR_REGION(val))
199  uint32_t rbar;
200
201#define ARMV7M_MPU_RASR_XN (1U << 28)
202#define ARMV7M_MPU_RASR_AP_SHIFT 24
203#define ARMV7M_MPU_RASR_AP_MASK \
204  ((0x7U) << ARMV7M_MPU_RASR_AP_SHIFT)
205#define ARMV7M_MPU_RASR_AP(val) \
206  (((val) << ARMV7M_MPU_RASR_AP_SHIFT) & ARMV7M_MPU_RASR_AP_MASK)
207#define ARMV7M_MPU_RASR_AP_GET(reg) \
208  (((val) & ARMV7M_MPU_RASR_AP_MASK) >> ARMV7M_MPU_RASR_AP_SHIFT)
209#define ARMV7M_MPU_RASR_AP_SET(reg, val) \
210  (((reg) & ~ARMV7M_MPU_RASR_AP_MASK) | ARMV7M_MPU_RASR_AP(val))
211#define ARMV7M_MPU_RASR_TEX_SHIFT 19
212#define ARMV7M_MPU_RASR_TEX_MASK \
213  ((0x7U) << ARMV7M_MPU_RASR_TEX_SHIFT)
214#define ARMV7M_MPU_RASR_TEX(val) \
215  (((val) << ARMV7M_MPU_RASR_TEX_SHIFT) & ARMV7M_MPU_RASR_TEX_MASK)
216#define ARMV7M_MPU_RASR_TEX_GET(reg) \
217  (((val) & ARMV7M_MPU_RASR_TEX_MASK) >> ARMV7M_MPU_RASR_TEX_SHIFT)
218#define ARMV7M_MPU_RASR_TEX_SET(reg, val) \
219  (((reg) & ~ARMV7M_MPU_RASR_TEX_MASK) | ARMV7M_MPU_RASR_TEX(val))
220#define ARMV7M_MPU_RASR_S (1U << 18)
221#define ARMV7M_MPU_RASR_C (1U << 17)
222#define ARMV7M_MPU_RASR_B (1U << 16)
223#define ARMV7M_MPU_RASR_SRD_SHIFT 8
224#define ARMV7M_MPU_RASR_SRD_MASK \
225  ((0xffU) << ARMV7M_MPU_RASR_SRD_SHIFT)
226#define ARMV7M_MPU_RASR_SRD(val) \
227  (((val) << ARMV7M_MPU_RASR_SRD_SHIFT) & ARMV7M_MPU_RASR_SRD_MASK)
228#define ARMV7M_MPU_RASR_SRD_GET(reg) \
229  (((val) & ARMV7M_MPU_RASR_SRD_MASK) >> ARMV7M_MPU_RASR_SRD_SHIFT)
230#define ARMV7M_MPU_RASR_SRD_SET(reg, val) \
231  (((reg) & ~ARMV7M_MPU_RASR_SRD_MASK) | ARMV7M_MPU_RASR_SRD(val))
232#define ARMV7M_MPU_RASR_SIZE_SHIFT 1
233#define ARMV7M_MPU_RASR_SIZE_MASK \
234  ((0x1fU) << ARMV7M_MPU_RASR_SIZE_SHIFT)
235#define ARMV7M_MPU_RASR_SIZE(val) \
236  (((val) << ARMV7M_MPU_RASR_SIZE_SHIFT) & ARMV7M_MPU_RASR_SIZE_MASK)
237#define ARMV7M_MPU_RASR_SIZE_GET(reg) \
238  (((val) & ARMV7M_MPU_RASR_SIZE_MASK) >> ARMV7M_MPU_RASR_SIZE_SHIFT)
239#define ARMV7M_MPU_RASR_SIZE_SET(reg, val) \
240  (((reg) & ~ARMV7M_MPU_RASR_SIZE_MASK) | ARMV7M_MPU_RASR_SIZE(val))
241#define ARMV7M_MPU_RASR_ENABLE (1U << 0)
242  uint32_t rasr;
243
244  uint32_t rbar_a1;
245  uint32_t rasr_a1;
246  uint32_t rbar_a2;
247  uint32_t rasr_a2;
248  uint32_t rbar_a3;
249  uint32_t rasr_a3;
250} ARMV7M_MPU;
251
252typedef enum {
253  ARMV7M_MPU_AP_PRIV_NO_USER_NO,
254  ARMV7M_MPU_AP_PRIV_RW_USER_NO,
255  ARMV7M_MPU_AP_PRIV_RW_USER_RO,
256  ARMV7M_MPU_AP_PRIV_RW_USER_RW,
257  ARMV7M_MPU_AP_PRIV_RO_USER_NO = 0x5,
258  ARMV7M_MPU_AP_PRIV_RO_USER_RO,
259} ARMV7M_MPU_Access_permissions;
260
261typedef enum {
262  ARMV7M_MPU_ATTR_R = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RO_USER_NO)
263    | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_XN,
264  ARMV7M_MPU_ATTR_RW = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO)
265    | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_XN | ARMV7M_MPU_RASR_B,
266  ARMV7M_MPU_ATTR_RWX = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO)
267    | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B,
268  ARMV7M_MPU_ATTR_X = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_NO_USER_NO)
269    | ARMV7M_MPU_RASR_C,
270  ARMV7M_MPU_ATTR_RX = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RO_USER_NO)
271    | ARMV7M_MPU_RASR_C,
272  ARMV7M_MPU_ATTR_IO = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO)
273    | ARMV7M_MPU_RASR_XN,
274} ARMV7M_MPU_Attributes;
275
276typedef enum {
277  ARMV7M_MPU_SIZE_32_B = 0x4,
278  ARMV7M_MPU_SIZE_64_B,
279  ARMV7M_MPU_SIZE_128_B,
280  ARMV7M_MPU_SIZE_256_B,
281  ARMV7M_MPU_SIZE_512_B,
282  ARMV7M_MPU_SIZE_1_KB,
283  ARMV7M_MPU_SIZE_2_KB,
284  ARMV7M_MPU_SIZE_4_KB,
285  ARMV7M_MPU_SIZE_8_KB,
286  ARMV7M_MPU_SIZE_16_KB,
287  ARMV7M_MPU_SIZE_32_KB,
288  ARMV7M_MPU_SIZE_64_KB,
289  ARMV7M_MPU_SIZE_128_KB,
290  ARMV7M_MPU_SIZE_256_KB,
291  ARMV7M_MPU_SIZE_512_KB,
292  ARMV7M_MPU_SIZE_1_MB,
293  ARMV7M_MPU_SIZE_2_MB,
294  ARMV7M_MPU_SIZE_4_MB,
295  ARMV7M_MPU_SIZE_8_MB,
296  ARMV7M_MPU_SIZE_16_MB,
297  ARMV7M_MPU_SIZE_32_MB,
298  ARMV7M_MPU_SIZE_64_MB,
299  ARMV7M_MPU_SIZE_128_MB,
300  ARMV7M_MPU_SIZE_256_MB,
301  ARMV7M_MPU_SIZE_512_MB,
302  ARMV7M_MPU_SIZE_1_GB,
303  ARMV7M_MPU_SIZE_2_GB,
304  ARMV7M_MPU_SIZE_4_GB
305} ARMV7M_MPU_Size;
306
307typedef struct {
308  uint32_t rbar;
309  uint32_t rasr;
310} ARMV7M_MPU_Region;
311
312#define ARMV7M_MPU_REGION_INITIALIZER(idx, addr, size, attr) \
313  { \
314    ((addr) & ARMV7M_MPU_RBAR_ADDR_MASK) \
315      | ARMV7M_MPU_RBAR_VALID \
316      | ARMV7M_MPU_RBAR_REGION(idx), \
317    ARMV7M_MPU_RASR_SIZE(size) | (attr) | ARMV7M_MPU_RASR_ENABLE \
318  }
319
320#define ARMV7M_MPU_REGION_DISABLED_INITIALIZER(idx) \
321  { \
322    ARMV7M_MPU_RBAR_VALID | ARMV7M_MPU_RBAR_REGION(idx), \
323    0 \
324  }
325
326#define ARMV7M_SCS_BASE 0xe000e000
327#define ARMV7M_ICTAC_BASE (ARMV7M_SCS_BASE + 0x0)
328#define ARMV7M_SYSTICK_BASE (ARMV7M_SCS_BASE + 0x10)
329#define ARMV7M_NVIC_BASE (ARMV7M_SCS_BASE + 0x100)
330#define ARMV7M_SCB_BASE (ARMV7M_SCS_BASE + 0xd00)
331#define ARMV7M_MPU_BASE (ARMV7M_SCS_BASE + 0xd90)
332
333#define _ARMV7M_ICTAC \
334  ((volatile ARMV7M_ICTAC *) ARMV7M_ICTAC_BASE)
335#define _ARMV7M_SCB \
336  ((volatile ARMV7M_SCB *) ARMV7M_SCB_BASE)
337#define _ARMV7M_Systick \
338  ((volatile ARMV7M_Systick *) ARMV7M_SYSTICK_BASE)
339#define _ARMV7M_NVIC \
340  ((volatile ARMV7M_NVIC *) ARMV7M_NVIC_BASE)
341#define _ARMV7M_MPU \
342  ((volatile ARMV7M_MPU *) ARMV7M_MPU_BASE)
343
344#define ARMV7M_VECTOR_MSP 0
345#define ARMV7M_VECTOR_RESET 1
346#define ARMV7M_VECTOR_NMI 2
347#define ARMV7M_VECTOR_HARD_FAULT 3
348#define ARMV7M_VECTOR_MEM_MANAGE 4
349#define ARMV7M_VECTOR_BUS_FAULT 5
350#define ARMV7M_VECTOR_USAGE_FAULT 6
351#define ARMV7M_VECTOR_SVC 11
352#define ARMV7M_VECTOR_DEBUG_MONITOR 12
353#define ARMV7M_VECTOR_PENDSV 14
354#define ARMV7M_VECTOR_SYSTICK 15
355#define ARMV7M_VECTOR_IRQ(n) ((n) + 16)
356#define ARMV7M_IRQ_OF_VECTOR(n) ((n) - 16)
357
358#define ARMV7M_EXCEPTION_PRIORITY_LOWEST 255
359
360static inline bool _ARMV7M_Is_vector_an_irq( int vector )
361{
362  return vector >= 16;
363}
364
365static inline uint32_t _ARMV7M_Get_basepri(void)
366{
367  uint32_t val;
368  __asm__ volatile ("mrs %[val], basepri\n" : [val] "=&r" (val));
369  return val;
370}
371
372static inline void _ARMV7M_Set_basepri(uint32_t val)
373{
374  __asm__ volatile ("msr basepri, %[val]\n" : : [val] "r" (val));
375}
376
377static inline uint32_t _ARMV7M_Get_primask(void)
378{
379  uint32_t val;
380  __asm__ volatile ("mrs %[val], primask\n" : [val] "=&r" (val));
381  return val;
382}
383
384static inline void _ARMV7M_Set_primask(uint32_t val)
385{
386  __asm__ volatile ("msr primask, %[val]\n" : : [val] "r" (val));
387}
388
389static inline uint32_t _ARMV7M_Get_faultmask(void)
390{
391  uint32_t val;
392  __asm__ volatile ("mrs %[val], faultmask\n" : [val] "=&r" (val));
393  return val;
394}
395
396static inline void _ARMV7M_Set_faultmask(uint32_t val)
397{
398  __asm__ volatile ("msr faultmask, %[val]\n" : : [val] "r" (val));
399}
400
401static inline uint32_t _ARMV7M_Get_control(void)
402{
403  uint32_t val;
404  __asm__ volatile ("mrs %[val], control\n" : [val] "=&r" (val));
405  return val;
406}
407
408static inline void _ARMV7M_Set_control(uint32_t val)
409{
410  __asm__ volatile ("msr control, %[val]\n" : : [val] "r" (val));
411}
412
413static inline uint32_t _ARMV7M_Get_MSP(void)
414{
415  uint32_t val;
416  __asm__ volatile ("mrs %[val], msp\n" : [val] "=&r" (val));
417  return val;
418}
419
420static inline void _ARMV7M_Set_MSP(uint32_t val)
421{
422  __asm__ volatile ("msr msp, %[val]\n" : : [val] "r" (val));
423}
424
425static inline uint32_t _ARMV7M_Get_PSP(void)
426{
427  uint32_t val;
428  __asm__ volatile ("mrs %[val], psp\n" : [val] "=&r" (val));
429  return val;
430}
431
432static inline void _ARMV7M_Set_PSP(uint32_t val)
433{
434  __asm__ volatile ("msr psp, %[val]\n" : : [val] "r" (val));
435}
436
437static inline uint32_t _ARMV7M_Get_XPSR(void)
438{
439  uint32_t val;
440  __asm__ volatile ("mrs %[val], xpsr\n" : [val] "=&r" (val));
441  return val;
442}
443
444static inline bool _ARMV7M_NVIC_Is_enabled( int irq )
445{
446  int index = irq >> 5;
447  uint32_t bit = 1U << (irq & 0x1f);
448
449  return (_ARMV7M_NVIC->iser [index] & bit) != 0;
450}
451
452static inline void _ARMV7M_NVIC_Set_enable( int irq )
453{
454  int index = irq >> 5;
455  uint32_t bit = 1U << (irq & 0x1f);
456
457  _ARMV7M_NVIC->iser [index] = bit;
458}
459
460static inline void _ARMV7M_NVIC_Clear_enable( int irq )
461{
462  int index = irq >> 5;
463  uint32_t bit = 1U << (irq & 0x1f);
464
465  _ARMV7M_NVIC->icer [index] = bit;
466}
467
468static inline bool _ARMV7M_NVIC_Is_pending( int irq )
469{
470  int index = irq >> 5;
471  uint32_t bit = 1U << (irq & 0x1f);
472
473  return (_ARMV7M_NVIC->ispr [index] & bit) != 0;
474}
475
476static inline void _ARMV7M_NVIC_Set_pending( int irq )
477{
478  int index = irq >> 5;
479  uint32_t bit = 1U << (irq & 0x1f);
480
481  _ARMV7M_NVIC->ispr [index] = bit;
482}
483
484static inline void _ARMV7M_NVIC_Clear_pending( int irq )
485{
486  int index = irq >> 5;
487  uint32_t bit = 1U << (irq & 0x1f);
488
489  _ARMV7M_NVIC->icpr [index] = bit;
490}
491
492static inline bool _ARMV7M_NVIC_Is_active( int irq )
493{
494  int index = irq >> 5;
495  uint32_t bit = 1U << (irq & 0x1f);
496
497  return (_ARMV7M_NVIC->iabr [index] & bit) != 0;
498}
499
500static inline void _ARMV7M_NVIC_Set_priority( int irq, int priority )
501{
502  _ARMV7M_NVIC->ipr [irq] = (uint8_t) priority;
503}
504
505static inline int _ARMV7M_NVIC_Get_priority( int irq )
506{
507  return _ARMV7M_NVIC->ipr [irq];
508}
509
510int _ARMV7M_Get_exception_priority( int vector );
511
512void _ARMV7M_Set_exception_priority( int vector, int priority );
513
514ARMV7M_Exception_handler _ARMV7M_Get_exception_handler( int index );
515
516void _ARMV7M_Set_exception_handler(
517  int index,
518  ARMV7M_Exception_handler handler
519);
520
521/**
522 * @brief ARMV7M set exception priority and handler.
523 */
524void _ARMV7M_Set_exception_priority_and_handler(
525  int index,
526  int priority,
527  ARMV7M_Exception_handler handler
528);
529
530void _ARMV7M_Exception_default( void );
531
532void _ARMV7M_Interrupt_service_enter( void );
533
534void _ARMV7M_Interrupt_service_leave( void );
535
536void _ARMV7M_Pendable_service_call( void );
537
538void _ARMV7M_Supervisor_call( void );
539
540#endif /* ASM */
541
542#endif /* ARM_MULTILIB_ARCH_V7M */
543
544#ifdef __cplusplus
545}
546#endif /* __cplusplus */
547
548#endif /* RTEMS_SCORE_ARMV7M_H */
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