source: rtems/cpukit/score/cpu/arm/include/rtems/score/paravirt.h @ c0443b4

5
Last change on this file since c0443b4 was c0443b4, checked in by Joel Sherrill <joel@…>, on Mar 12, 2018 at 7:42:47 PM

Add ARM Paravirtualization support

Closes #3305.

  • Property mode set to 100644
File size: 1.9 KB
Line 
1/**
2 * @file
3 *
4 * @brief ARM Paravirtualization Definitions
5 *
6 * This include file contains definitions pertaining to paravirtualization
7 * of the ARM port.
8 */
9
10/*
11 *  COPYRIGHT (c) 2018.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may in
15 *  the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19
20#ifndef RTEMS_PARAVIRT
21#error "This file should only be included with paravirtualization is enabled."
22#endif
23
24#ifndef _RTEMS_SCORE_PARAVIRT_H
25#define _RTEMS_SCORE_PARAVIRT_H
26
27/**
28 * @defgroup ParavirtARM Paravirtualization ARM Support
29 *
30 * @ingroup Score
31 *
32 * This handler encapulates the functionality (primarily conditional
33 * feature defines) related to paravirtualization on the ARM.
34 *
35 * Paravirtualization on the ARM makes the following assumptions:
36 *
37 *   - RTEMS executes in user space
38 *   - Interrupt enable/disable support using the MSR must be disabled
39 *     and replaced with BSP provided methods which are adapted to the
40 *     hosting environment.
41 */
42
43#ifndef ASM
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49#ifdef __cplusplus
50}
51#endif
52
53#endif  /* !ASM */
54
55/**
56 * In a paravirtualized environment, RTEMS executes in user space
57 * and cannot disable/enable external exceptions (e.g. interrupts).
58 * The BSP which acts as an adapter to the hosting environment will
59 * provide the interrupt enable/disable methods.
60 */
61#define ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE
62
63/**
64 * In a paravirtualized environment, RTEMS executes in user space
65 * and cannot write to the the Thread ID register which is normally
66 * used. CP15 C13 has three variants of a Thread ID register.
67 *
68 * - Opcode_2 = 2: This register is both user and privileged R/W accessible.
69 * - Opcode_2 = 3: This register is user read-only and privileged
70 *   R/W accessible.
71 * - Opcode_2 = 4: This register is privileged R/W accessible only.
72 */
73#define ARM_DISABLE_THREAD_ID_REGISTER_USE
74
75#endif
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