1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @brief CPU Port Implementation API |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2013, 2016 embedded brains GmbH |
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11 | * |
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12 | * Redistribution and use in source and binary forms, with or without |
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13 | * modification, are permitted provided that the following conditions |
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14 | * are met: |
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15 | * 1. Redistributions of source code must retain the above copyright |
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16 | * notice, this list of conditions and the following disclaimer. |
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17 | * 2. Redistributions in binary form must reproduce the above copyright |
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18 | * notice, this list of conditions and the following disclaimer in the |
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19 | * documentation and/or other materials provided with the distribution. |
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20 | * |
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21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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22 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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24 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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25 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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31 | * POSSIBILITY OF SUCH DAMAGE. |
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32 | */ |
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33 | |
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34 | #ifndef _RTEMS_SCORE_CPUIMPL_H |
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35 | #define _RTEMS_SCORE_CPUIMPL_H |
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36 | |
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37 | #include <rtems/score/cpu.h> |
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38 | |
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39 | /** |
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40 | * @defgroup RTEMSScoreCPUARM ARM |
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41 | * |
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42 | * @ingroup RTEMSScoreCPU |
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43 | * |
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44 | * @brief ARM Architecture Support |
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45 | * |
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46 | * @{ |
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47 | */ |
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48 | |
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49 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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50 | |
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51 | #ifdef ARM_MULTILIB_ARCH_V4 |
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52 | |
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53 | #if defined(ARM_MULTILIB_VFP_D32) |
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54 | #define CPU_INTERRUPT_FRAME_SIZE 240 |
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55 | #elif defined(ARM_MULTILIB_VFP) |
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56 | #define CPU_INTERRUPT_FRAME_SIZE 112 |
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57 | #else |
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58 | #define CPU_INTERRUPT_FRAME_SIZE 40 |
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59 | #endif |
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60 | |
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61 | #endif /* ARM_MULTILIB_ARCH_V4 */ |
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62 | |
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63 | #ifndef ASM |
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64 | |
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65 | #ifdef __cplusplus |
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66 | extern "C" { |
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67 | #endif |
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68 | |
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69 | #ifdef ARM_MULTILIB_ARCH_V4 |
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70 | |
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71 | typedef struct { |
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72 | #ifdef ARM_MULTILIB_VFP |
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73 | uint32_t fpscr; |
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74 | #ifdef ARM_MULTILIB_VFP_D32 |
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75 | double d16; |
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76 | double d17; |
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77 | double d18; |
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78 | double d19; |
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79 | double d20; |
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80 | double d21; |
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81 | double d22; |
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82 | double d23; |
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83 | double d24; |
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84 | double d25; |
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85 | double d26; |
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86 | double d27; |
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87 | double d28; |
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88 | double d29; |
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89 | double d30; |
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90 | double d31; |
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91 | #endif /* ARM_MULTILIB_VFP_D32 */ |
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92 | double d0; |
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93 | double d1; |
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94 | double d2; |
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95 | double d3; |
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96 | double d4; |
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97 | double d5; |
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98 | double d6; |
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99 | double d7; |
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100 | #endif /* ARM_MULTILIB_VFP */ |
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101 | #ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE |
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102 | uint32_t r0; |
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103 | uint32_t r1; |
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104 | uint32_t r2; |
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105 | uint32_t r3; |
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106 | uint32_t r7; |
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107 | uint32_t r9; |
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108 | uint32_t r12; |
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109 | uint32_t lr; |
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110 | uint32_t return_pc; |
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111 | uint32_t return_cpsr; |
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112 | #else /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */ |
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113 | uint32_t r9; |
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114 | uint32_t lr; |
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115 | uint32_t r0; |
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116 | uint32_t r1; |
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117 | uint32_t r2; |
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118 | uint32_t r3; |
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119 | uint32_t return_pc; |
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120 | uint32_t return_cpsr; |
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121 | uint32_t r7; |
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122 | uint32_t r12; |
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123 | #endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */ |
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124 | } CPU_Interrupt_frame; |
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125 | |
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126 | #ifdef RTEMS_SMP |
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127 | |
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128 | static inline struct Per_CPU_Control *_ARM_Get_current_per_CPU_control( void ) |
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129 | { |
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130 | struct Per_CPU_Control *cpu_self; |
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131 | |
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132 | /* Use PL1 only Thread ID Register (TPIDRPRW) */ |
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133 | __asm__ volatile ( |
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134 | "mrc p15, 0, %0, c13, c0, 4" |
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135 | : "=r" ( cpu_self ) |
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136 | ); |
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137 | |
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138 | return cpu_self; |
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139 | } |
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140 | |
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141 | #define _CPU_Get_current_per_CPU_control() _ARM_Get_current_per_CPU_control() |
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142 | |
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143 | #endif /* RTEMS_SMP */ |
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144 | |
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145 | #endif /* ARM_MULTILIB_ARCH_V4 */ |
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146 | |
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147 | RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); |
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148 | |
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149 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
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150 | |
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151 | void _CPU_Context_validate( uintptr_t pattern ); |
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152 | |
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153 | RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) |
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154 | { |
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155 | __asm__ volatile ( "udf" ); |
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156 | } |
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157 | |
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158 | RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) |
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159 | { |
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160 | __asm__ volatile ( "nop" ); |
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161 | } |
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162 | |
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163 | #ifdef __cplusplus |
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164 | } |
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165 | #endif |
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166 | |
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167 | #endif /* ASM */ |
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168 | |
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169 | /** @} */ |
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170 | |
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171 | #endif /* _RTEMS_SCORE_CPUIMPL_H */ |
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