source: rtems/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h @ 3a646426

5
Last change on this file since 3a646426 was 3a646426, checked in by Sebastian Huber <sebastian.huber@…>, on 07/19/18 at 10:53:34

score: Add _CPU_Instruction_illegal()

On some architectures/simulators it is difficult to provoke an
exception with misaligned or illegal data loads. Use an illegal
instruction instead.

Update #3433.
  • Property mode set to 100644
File size: 2.2 KB
Line 
1/**
2 * @file
3 *
4 * @brief CPU Port Implementation API
5 */
6
7/*
8 * Copyright (c) 2013, 2016 embedded brains GmbH
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#ifndef _RTEMS_SCORE_CPUIMPL_H
16#define _RTEMS_SCORE_CPUIMPL_H
17
18#include <rtems/score/cpu.h>
19
20#define CPU_PER_CPU_CONTROL_SIZE 0
21
22#ifdef ARM_MULTILIB_ARCH_V4
23
24#if defined(ARM_MULTILIB_VFP_D32)
25#define CPU_INTERRUPT_FRAME_SIZE 240
26#elif defined(ARM_MULTILIB_VFP)
27#define CPU_INTERRUPT_FRAME_SIZE 112
28#else
29#define CPU_INTERRUPT_FRAME_SIZE 40
30#endif
31
32#endif /* ARM_MULTILIB_ARCH_V4 */
33
34#ifndef ASM
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40#ifdef ARM_MULTILIB_ARCH_V4
41
42typedef struct {
43#ifdef ARM_MULTILIB_VFP
44  uint32_t fpscr;
45#ifdef ARM_MULTILIB_VFP_D32
46  double d16;
47  double d17;
48  double d18;
49  double d19;
50  double d20;
51  double d21;
52  double d22;
53  double d23;
54  double d24;
55  double d25;
56  double d26;
57  double d27;
58  double d28;
59  double d29;
60  double d30;
61  double d31;
62#endif /* ARM_MULTILIB_VFP_D32 */
63  double d0;
64  double d1;
65  double d2;
66  double d3;
67  double d4;
68  double d5;
69  double d6;
70  double d7;
71#endif /* ARM_MULTILIB_VFP */
72  uint32_t r9;
73  uint32_t lr;
74  uint32_t r0;
75  uint32_t r1;
76  uint32_t r2;
77  uint32_t r3;
78  uint32_t return_pc;
79  uint32_t return_cpsr;
80  uint32_t r7;
81  uint32_t r12;
82} CPU_Interrupt_frame;
83
84#ifdef RTEMS_SMP
85
86static inline struct Per_CPU_Control *_ARM_Get_current_per_CPU_control( void )
87{
88  struct Per_CPU_Control *cpu_self;
89
90  /* Use PL1 only Thread ID Register (TPIDRPRW) */
91  __asm__ volatile (
92    "mrc p15, 0, %0, c13, c0, 4"
93    : "=r" ( cpu_self )
94  );
95
96  return cpu_self;
97}
98
99#define _CPU_Get_current_per_CPU_control() _ARM_Get_current_per_CPU_control()
100
101#endif /* RTEMS_SMP */
102
103#endif /* ARM_MULTILIB_ARCH_V4 */
104
105void _CPU_Context_volatile_clobber( uintptr_t pattern );
106
107void _CPU_Context_validate( uintptr_t pattern );
108
109RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
110{
111  __asm__ volatile ( "udf" );
112}
113
114RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
115{
116  __asm__ volatile ( "nop" );
117}
118
119#ifdef __cplusplus
120}
121#endif
122
123#endif /* ASM */
124
125#endif /* _RTEMS_SCORE_CPUIMPL_H */
Note: See TracBrowser for help on using the repository browser.