source: rtems/cpukit/score/cpu/arm/include/rtems/score/cpu.h @ c0443b4

5
Last change on this file since c0443b4 was c0443b4, checked in by Joel Sherrill <joel@…>, on Mar 12, 2018 at 7:42:47 PM

Add ARM Paravirtualization support

Closes #3305.

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File size: 16.5 KB
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1/**
2 * @file
3 *
4 * @brief ARM Architecture Support API
5 */
6
7/*
8 *  This include file contains information pertaining to the ARM
9 *  processor.
10 *
11 *  Copyright (c) 2009, 2017 embedded brains GmbH
12 *
13 *  Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com>
14 *
15 *  Copyright (c) 2006 OAR Corporation
16 *
17 *  Copyright (c) 2002 Advent Networks, Inc.
18 *        Jay Monkman <jmonkman@adventnetworks.com>
19 *
20 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
21 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
22 *
23 *  The license and distribution terms for this file may be
24 *  found in the file LICENSE in this distribution or at
25 *  http://www.rtems.org/license/LICENSE.
26 *
27 */
28
29#ifndef _RTEMS_SCORE_CPU_H
30#define _RTEMS_SCORE_CPU_H
31
32#include <rtems/score/basedefs.h>
33#if defined(RTEMS_PARAVIRT)
34#include <rtems/score/paravirt.h>
35#endif
36#include <rtems/score/arm.h>
37
38#if defined(ARM_MULTILIB_ARCH_V4)
39
40/**
41 * @defgroup ScoreCPUARM ARM Specific Support
42 *
43 * @ingroup ScoreCPU
44 *
45 * @brief ARM specific support.
46 */
47/**@{**/
48
49#if defined(__thumb__) && !defined(__thumb2__)
50  #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg
51  #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n"
52  #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n"
53  #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg)
54  #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT
55#else
56  #define ARM_SWITCH_REGISTERS
57  #define ARM_SWITCH_TO_ARM
58  #define ARM_SWITCH_BACK
59  #define ARM_SWITCH_OUTPUT
60  #define ARM_SWITCH_ADDITIONAL_OUTPUT
61#endif
62
63/**
64 * @name Program Status Register
65 */
66/**@{**/
67
68#define ARM_PSR_N (1 << 31)
69#define ARM_PSR_Z (1 << 30)
70#define ARM_PSR_C (1 << 29)
71#define ARM_PSR_V (1 << 28)
72#define ARM_PSR_Q (1 << 27)
73#define ARM_PSR_J (1 << 24)
74#define ARM_PSR_GE_SHIFT 16
75#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT)
76#define ARM_PSR_E (1 << 9)
77#define ARM_PSR_A (1 << 8)
78#define ARM_PSR_I (1 << 7)
79#define ARM_PSR_F (1 << 6)
80#define ARM_PSR_T (1 << 5)
81#define ARM_PSR_M_SHIFT 0
82#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT)
83#define ARM_PSR_M_USR 0x10
84#define ARM_PSR_M_FIQ 0x11
85#define ARM_PSR_M_IRQ 0x12
86#define ARM_PSR_M_SVC 0x13
87#define ARM_PSR_M_ABT 0x17
88#define ARM_PSR_M_HYP 0x1a
89#define ARM_PSR_M_UND 0x1b
90#define ARM_PSR_M_SYS 0x1f
91
92/** @} */
93
94/** @} */
95
96#endif /* defined(ARM_MULTILIB_ARCH_V4) */
97
98/**
99 * @addtogroup ScoreCPU
100 */
101/**@{**/
102
103/*
104 *  The ARM uses the PIC interrupt model.
105 */
106#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
107
108#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
109
110#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
111
112#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
113
114#define CPU_ISR_PASSES_FRAME_POINTER FALSE
115
116#define CPU_HARDWARE_FP FALSE
117
118#define CPU_SOFTWARE_FP FALSE
119
120#define CPU_ALL_TASKS_ARE_FP FALSE
121
122#define CPU_IDLE_TASK_IS_FP FALSE
123
124#define CPU_USE_DEFERRED_FP_SWITCH FALSE
125
126#define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE
127
128#if defined(ARM_MULTILIB_HAS_WFI)
129  #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
130#else
131  #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
132#endif
133
134#define CPU_STACK_GROWS_UP FALSE
135
136#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64)
137  #define CPU_CACHE_LINE_BYTES 64
138#else
139  #define CPU_CACHE_LINE_BYTES 32
140#endif
141
142#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
143
144#define CPU_MODES_INTERRUPT_MASK 0x1
145
146#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
147
148#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
149
150#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
151
152#define CPU_STACK_MINIMUM_SIZE (1024 * 4)
153
154/* AAPCS, section 4.1, Fundamental Data Types */
155#define CPU_SIZEOF_POINTER 4
156
157/* AAPCS, section 4.1, Fundamental Data Types */
158#define CPU_ALIGNMENT 8
159
160#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
161
162/* AAPCS, section 4.3.1, Aggregates */
163#define CPU_PARTITION_ALIGNMENT 4
164
165/* AAPCS, section 5.2.1.2, Stack constraints at a public interface */
166#define CPU_STACK_ALIGNMENT 8
167
168/*
169 * Bitfield handler macros.
170 *
171 * If we had a particularly fast function for finding the first
172 * bit set in a word, it would go here. Since we don't (*), we'll
173 * just use the universal macros.
174 *
175 * (*) On ARM V5 and later, there's a CLZ function which could be
176 *     used to implement much quicker than the default macro.
177 */
178
179#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
180
181#define CPU_MAXIMUM_PROCESSORS 32
182
183/** @} */
184
185#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
186  #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44
187#endif
188
189#ifdef ARM_MULTILIB_VFP
190  #define ARM_CONTEXT_CONTROL_D8_OFFSET 48
191#endif
192
193#ifdef ARM_MULTILIB_ARCH_V4
194  #define ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 40
195#endif
196
197#ifdef RTEMS_SMP
198  #if defined(ARM_MULTILIB_VFP)
199    #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112
200  #elif defined(ARM_MULTILIB_HAS_THREAD_ID_REGISTER)
201    #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48
202  #else
203    #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 44
204  #endif
205#endif
206
207#define ARM_EXCEPTION_FRAME_SIZE 80
208
209#define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52
210
211#define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72
212
213#define ARM_VFP_CONTEXT_SIZE 264
214
215#ifndef ASM
216
217#ifdef __cplusplus
218extern "C" {
219#endif
220
221/**
222 * @addtogroup ScoreCPU
223 */
224/**@{**/
225
226typedef struct {
227#if defined(ARM_MULTILIB_ARCH_V4)
228  uint32_t register_r4;
229  uint32_t register_r5;
230  uint32_t register_r6;
231  uint32_t register_r7;
232  uint32_t register_r8;
233  uint32_t register_r9;
234  uint32_t register_r10;
235  uint32_t register_fp;
236  uint32_t register_sp;
237  uint32_t register_lr;
238  uint32_t isr_dispatch_disable;
239#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M)
240  uint32_t register_r4;
241  uint32_t register_r5;
242  uint32_t register_r6;
243  uint32_t register_r7;
244  uint32_t register_r8;
245  uint32_t register_r9;
246  uint32_t register_r10;
247  uint32_t register_r11;
248  void *register_lr;
249  void *register_sp;
250  uint32_t isr_nest_level;
251#else
252  void *register_sp;
253#endif
254#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
255  uint32_t thread_id;
256#endif
257#ifdef ARM_MULTILIB_VFP
258  uint64_t register_d8;
259  uint64_t register_d9;
260  uint64_t register_d10;
261  uint64_t register_d11;
262  uint64_t register_d12;
263  uint64_t register_d13;
264  uint64_t register_d14;
265  uint64_t register_d15;
266#endif
267#ifdef RTEMS_SMP
268  volatile bool is_executing;
269#endif
270} Context_Control;
271
272typedef struct {
273  /* Not supported */
274} Context_Control_fp;
275
276static inline void _ARM_Data_memory_barrier( void )
277{
278#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
279  __asm__ volatile ( "dmb" : : : "memory" );
280#else
281  RTEMS_COMPILER_MEMORY_BARRIER();
282#endif
283}
284
285static inline void _ARM_Data_synchronization_barrier( void )
286{
287#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
288  __asm__ volatile ( "dsb" : : : "memory" );
289#else
290  RTEMS_COMPILER_MEMORY_BARRIER();
291#endif
292}
293
294static inline void _ARM_Instruction_synchronization_barrier( void )
295{
296#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
297  __asm__ volatile ( "isb" : : : "memory" );
298#else
299  RTEMS_COMPILER_MEMORY_BARRIER();
300#endif
301}
302
303#if defined(ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE)
304uint32_t arm_interrupt_disable( void );
305void arm_interrupt_enable( uint32_t level );
306void arm_interrupt_flash( uint32_t level );
307#else
308static inline uint32_t arm_interrupt_disable( void )
309{
310  uint32_t level;
311
312#if defined(ARM_MULTILIB_ARCH_V4)
313  uint32_t arm_switch_reg;
314
315  /*
316   * Disable only normal interrupts (IRQ).
317   *
318   * In order to support fast interrupts (FIQ) such that they can do something
319   * useful, we have to disable the operating system support for FIQs.  Having
320   * operating system support for them would require that FIQs are disabled
321   * during critical sections of the operating system and application.  At this
322   * level IRQs and FIQs would be equal.  It is true that FIQs could interrupt
323   * the non critical sections of IRQs, so here they would have a small
324   * advantage.  Without operating system support, the FIQs can execute at any
325   * time (of course not during the service of another FIQ). If someone needs
326   * operating system support for a FIQ, she can trigger a software interrupt and
327   * service the request in a two-step process.
328   */
329  __asm__ volatile (
330    ARM_SWITCH_TO_ARM
331    "mrs %[level], cpsr\n"
332    "orr %[arm_switch_reg], %[level], #0x80\n"
333    "msr cpsr, %[arm_switch_reg]\n"
334    ARM_SWITCH_BACK
335    : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level)
336  );
337#elif defined(ARM_MULTILIB_ARCH_V7M)
338  uint32_t basepri = 0x80;
339
340  __asm__ volatile (
341    "mrs %[level], basepri\n"
342    "msr basepri_max, %[basepri]\n"
343    : [level] "=&r" (level)
344    : [basepri] "r" (basepri)
345  );
346#endif
347
348  return level;
349}
350
351static inline void arm_interrupt_enable( uint32_t level )
352{
353#if defined(ARM_MULTILIB_ARCH_V4)
354  ARM_SWITCH_REGISTERS;
355
356  __asm__ volatile (
357    ARM_SWITCH_TO_ARM
358    "msr cpsr, %[level]\n"
359    ARM_SWITCH_BACK
360    : ARM_SWITCH_OUTPUT
361    : [level] "r" (level)
362  );
363#elif defined(ARM_MULTILIB_ARCH_V7M)
364  __asm__ volatile (
365    "msr basepri, %[level]\n"
366    :
367    : [level] "r" (level)
368  );
369#endif
370}
371
372static inline void arm_interrupt_flash( uint32_t level )
373{
374#if defined(ARM_MULTILIB_ARCH_V4)
375  uint32_t arm_switch_reg;
376
377  __asm__ volatile (
378    ARM_SWITCH_TO_ARM
379    "mrs %[arm_switch_reg], cpsr\n"
380    "msr cpsr, %[level]\n"
381    "msr cpsr, %[arm_switch_reg]\n"
382    ARM_SWITCH_BACK
383    : [arm_switch_reg] "=&r" (arm_switch_reg)
384    : [level] "r" (level)
385  );
386#elif defined(ARM_MULTILIB_ARCH_V7M)
387  uint32_t basepri;
388
389  __asm__ volatile (
390    "mrs %[basepri], basepri\n"
391    "msr basepri, %[level]\n"
392    "msr basepri, %[basepri]\n"
393    : [basepri] "=&r" (basepri)
394    : [level] "r" (level)
395  );
396#endif
397}
398#endif  /* !ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE */
399
400#define _CPU_ISR_Disable( _isr_cookie ) \
401  do { \
402    _isr_cookie = arm_interrupt_disable(); \
403  } while (0)
404
405#define _CPU_ISR_Enable( _isr_cookie )  \
406  arm_interrupt_enable( _isr_cookie )
407
408#define _CPU_ISR_Flash( _isr_cookie ) \
409  arm_interrupt_flash( _isr_cookie )
410
411RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
412{
413#if defined(ARM_MULTILIB_ARCH_V4)
414  return ( level & 0x80 ) == 0;
415#elif defined(ARM_MULTILIB_ARCH_V7M)
416  return level == 0;
417#endif
418}
419
420void _CPU_ISR_Set_level( uint32_t level );
421
422uint32_t _CPU_ISR_Get_level( void );
423
424void _CPU_Context_Initialize(
425  Context_Control *the_context,
426  void *stack_area_begin,
427  size_t stack_area_size,
428  uint32_t new_level,
429  void (*entry_point)( void ),
430  bool is_fp,
431  void *tls_area
432);
433
434#define _CPU_Context_Get_SP( _context ) \
435  (_context)->register_sp
436
437#ifdef RTEMS_SMP
438  static inline bool _CPU_Context_Get_is_executing(
439    const Context_Control *context
440  )
441  {
442    return context->is_executing;
443  }
444
445  static inline void _CPU_Context_Set_is_executing(
446    Context_Control *context,
447    bool is_executing
448  )
449  {
450    context->is_executing = is_executing;
451  }
452#endif
453
454#define _CPU_Context_Restart_self( _the_context ) \
455   _CPU_Context_restore( (_the_context) );
456
457#define _CPU_Context_Initialize_fp( _destination ) \
458  do { \
459    *(*(_destination)) = _CPU_Null_fp_context; \
460  } while (0)
461
462#define _CPU_Fatal_halt( _source, _err )    \
463   do {                                     \
464     uint32_t _level;                       \
465     uint32_t _error = _err;                \
466     _CPU_ISR_Disable( _level );            \
467     (void) _level;                         \
468     __asm__ volatile ("mov r0, %0\n"       \
469                   : "=r" (_error)          \
470                   : "0" (_error)           \
471                   : "r0" );                \
472     while (1);                             \
473   } while (0);
474
475/**
476 * @brief CPU initialization.
477 */
478void _CPU_Initialize( void );
479
480void _CPU_ISR_install_vector(
481  uint32_t vector,
482  proc_ptr new_handler,
483  proc_ptr *old_handler
484);
485
486/**
487 * @brief CPU switch context.
488 */
489void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
490
491void _CPU_Context_restore( Context_Control *new_context )
492  RTEMS_NO_RETURN;
493
494#if defined(ARM_MULTILIB_ARCH_V7M)
495  void _ARMV7M_Start_multitasking( Context_Control *heir )
496    RTEMS_NO_RETURN;
497  #define _CPU_Start_multitasking _ARMV7M_Start_multitasking
498#endif
499
500void _CPU_Context_volatile_clobber( uintptr_t pattern );
501
502void _CPU_Context_validate( uintptr_t pattern );
503
504#ifdef RTEMS_SMP
505  uint32_t _CPU_SMP_Initialize( void );
506
507  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
508
509  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
510
511  void _CPU_SMP_Prepare_start_multitasking( void );
512
513  static inline uint32_t _CPU_SMP_Get_current_processor( void )
514  {
515    uint32_t mpidr;
516
517    /* Use ARMv7 Multiprocessor Affinity Register (MPIDR) */
518    __asm__ volatile (
519      "mrc p15, 0, %[mpidr], c0, c0, 5\n"
520      : [mpidr] "=&r" (mpidr)
521    );
522
523    return mpidr & 0xffU;
524  }
525
526  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
527
528  static inline void _ARM_Send_event( void )
529  {
530    __asm__ volatile ( "sev" : : : "memory" );
531  }
532
533  static inline void _ARM_Wait_for_event( void )
534  {
535    __asm__ volatile ( "wfe" : : : "memory" );
536  }
537
538  static inline void _CPU_SMP_Processor_event_broadcast( void )
539  {
540    _ARM_Data_synchronization_barrier();
541    _ARM_Send_event();
542  }
543
544  static inline void _CPU_SMP_Processor_event_receive( void )
545  {
546    _ARM_Wait_for_event();
547    _ARM_Data_memory_barrier();
548  }
549#endif
550
551
552static inline uint32_t CPU_swap_u32( uint32_t value )
553{
554#if defined(__thumb2__)
555  __asm__ volatile (
556    "rev %0, %0"
557    : "=r" (value)
558    : "0" (value)
559  );
560  return value;
561#elif defined(__thumb__)
562  uint32_t byte1, byte2, byte3, byte4, swapped;
563
564  byte4 = (value >> 24) & 0xff;
565  byte3 = (value >> 16) & 0xff;
566  byte2 = (value >> 8)  & 0xff;
567  byte1 =  value & 0xff;
568
569  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
570  return swapped;
571#else
572  uint32_t tmp = value; /* make compiler warnings go away */
573  __asm__ volatile ("EOR %1, %0, %0, ROR #16\n"
574                "BIC %1, %1, #0xff0000\n"
575                "MOV %0, %0, ROR #8\n"
576                "EOR %0, %0, %1, LSR #8\n"
577                : "=r" (value), "=r" (tmp)
578                : "0" (value), "1" (tmp));
579  return value;
580#endif
581}
582
583static inline uint16_t CPU_swap_u16( uint16_t value )
584{
585#if defined(__thumb2__)
586  __asm__ volatile (
587    "rev16 %0, %0"
588    : "=r" (value)
589    : "0" (value)
590  );
591  return value;
592#else
593  return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU));
594#endif
595}
596
597typedef uint32_t CPU_Counter_ticks;
598
599CPU_Counter_ticks _CPU_Counter_read( void );
600
601CPU_Counter_ticks _CPU_Counter_difference(
602  CPU_Counter_ticks second,
603  CPU_Counter_ticks first
604);
605
606#if CPU_PROVIDES_IDLE_THREAD_BODY == TRUE
607  void *_CPU_Thread_Idle_body( uintptr_t ignored );
608#endif
609
610/** @} */
611
612/**
613 * @addtogroup ScoreCPUARM
614 */
615/**@{**/
616
617#if defined(ARM_MULTILIB_ARCH_V4)
618
619typedef enum {
620  ARM_EXCEPTION_RESET = 0,
621  ARM_EXCEPTION_UNDEF = 1,
622  ARM_EXCEPTION_SWI = 2,
623  ARM_EXCEPTION_PREF_ABORT = 3,
624  ARM_EXCEPTION_DATA_ABORT = 4,
625  ARM_EXCEPTION_RESERVED = 5,
626  ARM_EXCEPTION_IRQ = 6,
627  ARM_EXCEPTION_FIQ = 7,
628  MAX_EXCEPTIONS = 8,
629  ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff
630} Arm_symbolic_exception_name;
631
632#endif /* defined(ARM_MULTILIB_ARCH_V4) */
633
634typedef struct {
635  uint32_t register_fpexc;
636  uint32_t register_fpscr;
637  uint64_t register_d0;
638  uint64_t register_d1;
639  uint64_t register_d2;
640  uint64_t register_d3;
641  uint64_t register_d4;
642  uint64_t register_d5;
643  uint64_t register_d6;
644  uint64_t register_d7;
645  uint64_t register_d8;
646  uint64_t register_d9;
647  uint64_t register_d10;
648  uint64_t register_d11;
649  uint64_t register_d12;
650  uint64_t register_d13;
651  uint64_t register_d14;
652  uint64_t register_d15;
653  uint64_t register_d16;
654  uint64_t register_d17;
655  uint64_t register_d18;
656  uint64_t register_d19;
657  uint64_t register_d20;
658  uint64_t register_d21;
659  uint64_t register_d22;
660  uint64_t register_d23;
661  uint64_t register_d24;
662  uint64_t register_d25;
663  uint64_t register_d26;
664  uint64_t register_d27;
665  uint64_t register_d28;
666  uint64_t register_d29;
667  uint64_t register_d30;
668  uint64_t register_d31;
669} ARM_VFP_context;
670
671typedef struct {
672  uint32_t register_r0;
673  uint32_t register_r1;
674  uint32_t register_r2;
675  uint32_t register_r3;
676  uint32_t register_r4;
677  uint32_t register_r5;
678  uint32_t register_r6;
679  uint32_t register_r7;
680  uint32_t register_r8;
681  uint32_t register_r9;
682  uint32_t register_r10;
683  uint32_t register_r11;
684  uint32_t register_r12;
685  uint32_t register_sp;
686  void *register_lr;
687  void *register_pc;
688#if defined(ARM_MULTILIB_ARCH_V4)
689  uint32_t register_cpsr;
690  Arm_symbolic_exception_name vector;
691#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M)
692  uint32_t register_xpsr;
693  uint32_t vector;
694#endif
695  const ARM_VFP_context *vfp_context;
696  uint32_t reserved_for_stack_alignment;
697} CPU_Exception_frame;
698
699void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
700
701void _ARM_Exception_default( CPU_Exception_frame *frame );
702
703/** @} */
704
705/** Type that can store a 32-bit integer or a pointer. */
706typedef uintptr_t CPU_Uint32ptr;
707
708#ifdef __cplusplus
709}
710#endif
711
712#endif /* ASM */
713
714#endif /* _RTEMS_SCORE_CPU_H */
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