1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief ARM Architecture Support API |
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5 | */ |
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6 | |
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7 | /* |
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8 | * This include file contains information pertaining to the ARM |
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9 | * processor. |
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10 | * |
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11 | * Copyright (c) 2009, 2017 embedded brains GmbH |
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12 | * |
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13 | * Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com> |
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14 | * |
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15 | * Copyright (c) 2006 OAR Corporation |
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16 | * |
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17 | * Copyright (c) 2002 Advent Networks, Inc. |
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18 | * Jay Monkman <jmonkman@adventnetworks.com> |
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19 | * |
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20 | * COPYRIGHT (c) 2000 Canon Research Centre France SA. |
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21 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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22 | * |
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23 | * The license and distribution terms for this file may be |
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24 | * found in the file LICENSE in this distribution or at |
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25 | * http://www.rtems.org/license/LICENSE. |
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26 | * |
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27 | */ |
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28 | |
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29 | #ifndef _RTEMS_SCORE_CPU_H |
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30 | #define _RTEMS_SCORE_CPU_H |
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31 | |
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32 | #include <rtems/score/basedefs.h> |
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33 | #if defined(RTEMS_PARAVIRT) |
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34 | #include <rtems/score/paravirt.h> |
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35 | #endif |
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36 | #include <rtems/score/arm.h> |
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37 | |
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38 | #if defined(ARM_MULTILIB_ARCH_V4) |
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39 | |
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40 | /** |
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41 | * @defgroup ScoreCPUARM ARM Specific Support |
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42 | * |
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43 | * @ingroup ScoreCPU |
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44 | * |
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45 | * @brief ARM specific support. |
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46 | */ |
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47 | /**@{**/ |
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48 | |
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49 | #if defined(__thumb__) && !defined(__thumb2__) |
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50 | #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg |
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51 | #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n" |
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52 | #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n" |
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53 | #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg) |
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54 | #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT |
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55 | #else |
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56 | #define ARM_SWITCH_REGISTERS |
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57 | #define ARM_SWITCH_TO_ARM |
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58 | #define ARM_SWITCH_BACK |
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59 | #define ARM_SWITCH_OUTPUT |
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60 | #define ARM_SWITCH_ADDITIONAL_OUTPUT |
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61 | #endif |
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62 | |
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63 | /** |
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64 | * @name Program Status Register |
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65 | */ |
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66 | /**@{**/ |
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67 | |
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68 | #define ARM_PSR_N (1 << 31) |
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69 | #define ARM_PSR_Z (1 << 30) |
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70 | #define ARM_PSR_C (1 << 29) |
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71 | #define ARM_PSR_V (1 << 28) |
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72 | #define ARM_PSR_Q (1 << 27) |
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73 | #define ARM_PSR_J (1 << 24) |
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74 | #define ARM_PSR_GE_SHIFT 16 |
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75 | #define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT) |
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76 | #define ARM_PSR_E (1 << 9) |
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77 | #define ARM_PSR_A (1 << 8) |
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78 | #define ARM_PSR_I (1 << 7) |
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79 | #define ARM_PSR_F (1 << 6) |
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80 | #define ARM_PSR_T (1 << 5) |
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81 | #define ARM_PSR_M_SHIFT 0 |
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82 | #define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT) |
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83 | #define ARM_PSR_M_USR 0x10 |
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84 | #define ARM_PSR_M_FIQ 0x11 |
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85 | #define ARM_PSR_M_IRQ 0x12 |
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86 | #define ARM_PSR_M_SVC 0x13 |
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87 | #define ARM_PSR_M_ABT 0x17 |
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88 | #define ARM_PSR_M_HYP 0x1a |
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89 | #define ARM_PSR_M_UND 0x1b |
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90 | #define ARM_PSR_M_SYS 0x1f |
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91 | |
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92 | /** @} */ |
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93 | |
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94 | /** @} */ |
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95 | |
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96 | #endif /* defined(ARM_MULTILIB_ARCH_V4) */ |
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97 | |
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98 | /** |
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99 | * @addtogroup ScoreCPU |
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100 | */ |
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101 | /**@{**/ |
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102 | |
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103 | /* |
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104 | * The ARM uses the PIC interrupt model. |
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105 | */ |
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106 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
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107 | |
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108 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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109 | |
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110 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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111 | |
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112 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
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113 | |
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114 | #define CPU_ISR_PASSES_FRAME_POINTER FALSE |
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115 | |
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116 | #define CPU_HARDWARE_FP FALSE |
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117 | |
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118 | #define CPU_SOFTWARE_FP FALSE |
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119 | |
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120 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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121 | |
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122 | #define CPU_IDLE_TASK_IS_FP FALSE |
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123 | |
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124 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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125 | |
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126 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE |
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127 | |
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128 | #if defined(ARM_MULTILIB_HAS_WFI) |
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129 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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130 | #else |
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131 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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132 | #endif |
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133 | |
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134 | #define CPU_STACK_GROWS_UP FALSE |
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135 | |
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136 | #if defined(ARM_MULTILIB_CACHE_LINE_MAX_64) |
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137 | #define CPU_CACHE_LINE_BYTES 64 |
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138 | #else |
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139 | #define CPU_CACHE_LINE_BYTES 32 |
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140 | #endif |
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141 | |
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142 | #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
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143 | |
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144 | #define CPU_MODES_INTERRUPT_MASK 0x1 |
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145 | |
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146 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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147 | |
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148 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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149 | |
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150 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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151 | |
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152 | #define CPU_STACK_MINIMUM_SIZE (1024 * 4) |
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153 | |
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154 | /* AAPCS, section 4.1, Fundamental Data Types */ |
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155 | #define CPU_SIZEOF_POINTER 4 |
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156 | |
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157 | /* AAPCS, section 4.1, Fundamental Data Types */ |
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158 | #define CPU_ALIGNMENT 8 |
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159 | |
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160 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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161 | |
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162 | /* AAPCS, section 4.3.1, Aggregates */ |
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163 | #define CPU_PARTITION_ALIGNMENT 4 |
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164 | |
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165 | /* AAPCS, section 5.2.1.2, Stack constraints at a public interface */ |
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166 | #define CPU_STACK_ALIGNMENT 8 |
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167 | |
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168 | /* |
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169 | * Bitfield handler macros. |
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170 | * |
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171 | * If we had a particularly fast function for finding the first |
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172 | * bit set in a word, it would go here. Since we don't (*), we'll |
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173 | * just use the universal macros. |
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174 | * |
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175 | * (*) On ARM V5 and later, there's a CLZ function which could be |
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176 | * used to implement much quicker than the default macro. |
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177 | */ |
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178 | |
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179 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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180 | |
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181 | #define CPU_MAXIMUM_PROCESSORS 32 |
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182 | |
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183 | /** @} */ |
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184 | |
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185 | #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER |
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186 | #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44 |
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187 | #endif |
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188 | |
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189 | #ifdef ARM_MULTILIB_VFP |
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190 | #define ARM_CONTEXT_CONTROL_D8_OFFSET 48 |
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191 | #endif |
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192 | |
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193 | #ifdef ARM_MULTILIB_ARCH_V4 |
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194 | #define ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 40 |
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195 | #endif |
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196 | |
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197 | #ifdef RTEMS_SMP |
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198 | #if defined(ARM_MULTILIB_VFP) |
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199 | #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112 |
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200 | #elif defined(ARM_MULTILIB_HAS_THREAD_ID_REGISTER) |
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201 | #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48 |
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202 | #else |
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203 | #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 44 |
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204 | #endif |
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205 | #endif |
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206 | |
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207 | #define ARM_EXCEPTION_FRAME_SIZE 80 |
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208 | |
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209 | #define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52 |
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210 | |
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211 | #define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72 |
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212 | |
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213 | #define ARM_VFP_CONTEXT_SIZE 264 |
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214 | |
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215 | #ifndef ASM |
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216 | |
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217 | #ifdef __cplusplus |
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218 | extern "C" { |
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219 | #endif |
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220 | |
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221 | /** |
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222 | * @addtogroup ScoreCPU |
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223 | */ |
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224 | /**@{**/ |
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225 | |
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226 | typedef struct { |
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227 | #if defined(ARM_MULTILIB_ARCH_V4) |
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228 | uint32_t register_r4; |
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229 | uint32_t register_r5; |
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230 | uint32_t register_r6; |
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231 | uint32_t register_r7; |
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232 | uint32_t register_r8; |
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233 | uint32_t register_r9; |
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234 | uint32_t register_r10; |
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235 | uint32_t register_fp; |
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236 | uint32_t register_sp; |
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237 | uint32_t register_lr; |
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238 | uint32_t isr_dispatch_disable; |
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239 | #elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) |
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240 | uint32_t register_r4; |
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241 | uint32_t register_r5; |
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242 | uint32_t register_r6; |
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243 | uint32_t register_r7; |
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244 | uint32_t register_r8; |
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245 | uint32_t register_r9; |
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246 | uint32_t register_r10; |
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247 | uint32_t register_r11; |
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248 | void *register_lr; |
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249 | void *register_sp; |
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250 | uint32_t isr_nest_level; |
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251 | #else |
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252 | void *register_sp; |
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253 | #endif |
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254 | #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER |
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255 | uint32_t thread_id; |
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256 | #endif |
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257 | #ifdef ARM_MULTILIB_VFP |
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258 | uint64_t register_d8; |
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259 | uint64_t register_d9; |
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260 | uint64_t register_d10; |
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261 | uint64_t register_d11; |
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262 | uint64_t register_d12; |
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263 | uint64_t register_d13; |
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264 | uint64_t register_d14; |
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265 | uint64_t register_d15; |
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266 | #endif |
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267 | #ifdef RTEMS_SMP |
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268 | volatile bool is_executing; |
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269 | #endif |
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270 | } Context_Control; |
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271 | |
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272 | typedef struct { |
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273 | /* Not supported */ |
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274 | } Context_Control_fp; |
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275 | |
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276 | static inline void _ARM_Data_memory_barrier( void ) |
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277 | { |
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278 | #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS |
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279 | __asm__ volatile ( "dmb" : : : "memory" ); |
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280 | #else |
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281 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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282 | #endif |
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283 | } |
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284 | |
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285 | static inline void _ARM_Data_synchronization_barrier( void ) |
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286 | { |
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287 | #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS |
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288 | __asm__ volatile ( "dsb" : : : "memory" ); |
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289 | #else |
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290 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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291 | #endif |
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292 | } |
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293 | |
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294 | static inline void _ARM_Instruction_synchronization_barrier( void ) |
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295 | { |
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296 | #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS |
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297 | __asm__ volatile ( "isb" : : : "memory" ); |
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298 | #else |
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299 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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300 | #endif |
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301 | } |
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302 | |
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303 | #if defined(ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE) |
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304 | uint32_t arm_interrupt_disable( void ); |
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305 | void arm_interrupt_enable( uint32_t level ); |
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306 | void arm_interrupt_flash( uint32_t level ); |
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307 | #else |
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308 | static inline uint32_t arm_interrupt_disable( void ) |
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309 | { |
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310 | uint32_t level; |
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311 | |
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312 | #if defined(ARM_MULTILIB_ARCH_V4) |
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313 | uint32_t arm_switch_reg; |
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314 | |
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315 | /* |
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316 | * Disable only normal interrupts (IRQ). |
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317 | * |
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318 | * In order to support fast interrupts (FIQ) such that they can do something |
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319 | * useful, we have to disable the operating system support for FIQs. Having |
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320 | * operating system support for them would require that FIQs are disabled |
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321 | * during critical sections of the operating system and application. At this |
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322 | * level IRQs and FIQs would be equal. It is true that FIQs could interrupt |
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323 | * the non critical sections of IRQs, so here they would have a small |
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324 | * advantage. Without operating system support, the FIQs can execute at any |
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325 | * time (of course not during the service of another FIQ). If someone needs |
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326 | * operating system support for a FIQ, she can trigger a software interrupt and |
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327 | * service the request in a two-step process. |
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328 | */ |
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329 | __asm__ volatile ( |
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330 | ARM_SWITCH_TO_ARM |
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331 | "mrs %[level], cpsr\n" |
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332 | "orr %[arm_switch_reg], %[level], #0x80\n" |
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333 | "msr cpsr, %[arm_switch_reg]\n" |
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334 | ARM_SWITCH_BACK |
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335 | : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level) |
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336 | ); |
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337 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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338 | uint32_t basepri = 0x80; |
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339 | |
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340 | __asm__ volatile ( |
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341 | "mrs %[level], basepri\n" |
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342 | "msr basepri_max, %[basepri]\n" |
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343 | : [level] "=&r" (level) |
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344 | : [basepri] "r" (basepri) |
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345 | ); |
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346 | #endif |
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347 | |
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348 | return level; |
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349 | } |
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350 | |
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351 | static inline void arm_interrupt_enable( uint32_t level ) |
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352 | { |
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353 | #if defined(ARM_MULTILIB_ARCH_V4) |
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354 | ARM_SWITCH_REGISTERS; |
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355 | |
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356 | __asm__ volatile ( |
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357 | ARM_SWITCH_TO_ARM |
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358 | "msr cpsr, %[level]\n" |
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359 | ARM_SWITCH_BACK |
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360 | : ARM_SWITCH_OUTPUT |
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361 | : [level] "r" (level) |
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362 | ); |
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363 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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364 | __asm__ volatile ( |
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365 | "msr basepri, %[level]\n" |
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366 | : |
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367 | : [level] "r" (level) |
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368 | ); |
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369 | #endif |
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370 | } |
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371 | |
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372 | static inline void arm_interrupt_flash( uint32_t level ) |
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373 | { |
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374 | #if defined(ARM_MULTILIB_ARCH_V4) |
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375 | uint32_t arm_switch_reg; |
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376 | |
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377 | __asm__ volatile ( |
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378 | ARM_SWITCH_TO_ARM |
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379 | "mrs %[arm_switch_reg], cpsr\n" |
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380 | "msr cpsr, %[level]\n" |
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381 | "msr cpsr, %[arm_switch_reg]\n" |
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382 | ARM_SWITCH_BACK |
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383 | : [arm_switch_reg] "=&r" (arm_switch_reg) |
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384 | : [level] "r" (level) |
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385 | ); |
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386 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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387 | uint32_t basepri; |
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388 | |
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389 | __asm__ volatile ( |
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390 | "mrs %[basepri], basepri\n" |
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391 | "msr basepri, %[level]\n" |
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392 | "msr basepri, %[basepri]\n" |
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393 | : [basepri] "=&r" (basepri) |
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394 | : [level] "r" (level) |
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395 | ); |
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396 | #endif |
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397 | } |
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398 | #endif /* !ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE */ |
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399 | |
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400 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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401 | do { \ |
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402 | _isr_cookie = arm_interrupt_disable(); \ |
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403 | } while (0) |
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404 | |
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405 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
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406 | arm_interrupt_enable( _isr_cookie ) |
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407 | |
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408 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
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409 | arm_interrupt_flash( _isr_cookie ) |
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410 | |
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411 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
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412 | { |
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413 | #if defined(ARM_MULTILIB_ARCH_V4) |
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414 | return ( level & 0x80 ) == 0; |
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415 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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416 | return level == 0; |
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417 | #endif |
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418 | } |
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419 | |
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420 | void _CPU_ISR_Set_level( uint32_t level ); |
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421 | |
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422 | uint32_t _CPU_ISR_Get_level( void ); |
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423 | |
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424 | void _CPU_Context_Initialize( |
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425 | Context_Control *the_context, |
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426 | void *stack_area_begin, |
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427 | size_t stack_area_size, |
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428 | uint32_t new_level, |
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429 | void (*entry_point)( void ), |
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430 | bool is_fp, |
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431 | void *tls_area |
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432 | ); |
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433 | |
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434 | #define _CPU_Context_Get_SP( _context ) \ |
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435 | (_context)->register_sp |
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436 | |
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437 | #ifdef RTEMS_SMP |
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438 | static inline bool _CPU_Context_Get_is_executing( |
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439 | const Context_Control *context |
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440 | ) |
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441 | { |
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442 | return context->is_executing; |
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443 | } |
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444 | |
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445 | static inline void _CPU_Context_Set_is_executing( |
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446 | Context_Control *context, |
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447 | bool is_executing |
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448 | ) |
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449 | { |
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450 | context->is_executing = is_executing; |
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451 | } |
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452 | #endif |
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453 | |
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454 | #define _CPU_Context_Restart_self( _the_context ) \ |
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455 | _CPU_Context_restore( (_the_context) ); |
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456 | |
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457 | #define _CPU_Context_Initialize_fp( _destination ) \ |
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458 | do { \ |
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459 | *(*(_destination)) = _CPU_Null_fp_context; \ |
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460 | } while (0) |
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461 | |
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462 | #define _CPU_Fatal_halt( _source, _err ) \ |
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463 | do { \ |
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464 | uint32_t _level; \ |
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465 | uint32_t _error = _err; \ |
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466 | _CPU_ISR_Disable( _level ); \ |
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467 | (void) _level; \ |
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468 | __asm__ volatile ("mov r0, %0\n" \ |
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469 | : "=r" (_error) \ |
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470 | : "0" (_error) \ |
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471 | : "r0" ); \ |
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472 | while (1); \ |
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473 | } while (0); |
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474 | |
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475 | /** |
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476 | * @brief CPU initialization. |
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477 | */ |
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478 | void _CPU_Initialize( void ); |
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479 | |
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480 | void _CPU_ISR_install_vector( |
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481 | uint32_t vector, |
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482 | proc_ptr new_handler, |
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483 | proc_ptr *old_handler |
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484 | ); |
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485 | |
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486 | /** |
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487 | * @brief CPU switch context. |
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488 | */ |
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489 | void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); |
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490 | |
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491 | void _CPU_Context_restore( Context_Control *new_context ) |
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492 | RTEMS_NO_RETURN; |
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493 | |
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494 | #if defined(ARM_MULTILIB_ARCH_V7M) |
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495 | void _ARMV7M_Start_multitasking( Context_Control *heir ) |
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496 | RTEMS_NO_RETURN; |
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497 | #define _CPU_Start_multitasking _ARMV7M_Start_multitasking |
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498 | #endif |
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499 | |
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500 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
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501 | |
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502 | void _CPU_Context_validate( uintptr_t pattern ); |
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503 | |
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504 | #ifdef RTEMS_SMP |
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505 | uint32_t _CPU_SMP_Initialize( void ); |
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506 | |
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507 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
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508 | |
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509 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
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510 | |
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511 | void _CPU_SMP_Prepare_start_multitasking( void ); |
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512 | |
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513 | static inline uint32_t _CPU_SMP_Get_current_processor( void ) |
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514 | { |
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515 | uint32_t mpidr; |
---|
516 | |
---|
517 | /* Use ARMv7 Multiprocessor Affinity Register (MPIDR) */ |
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518 | __asm__ volatile ( |
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519 | "mrc p15, 0, %[mpidr], c0, c0, 5\n" |
---|
520 | : [mpidr] "=&r" (mpidr) |
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521 | ); |
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522 | |
---|
523 | return mpidr & 0xffU; |
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524 | } |
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525 | |
---|
526 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
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527 | |
---|
528 | static inline void _ARM_Send_event( void ) |
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529 | { |
---|
530 | __asm__ volatile ( "sev" : : : "memory" ); |
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531 | } |
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532 | |
---|
533 | static inline void _ARM_Wait_for_event( void ) |
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534 | { |
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535 | __asm__ volatile ( "wfe" : : : "memory" ); |
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536 | } |
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537 | |
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538 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
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539 | { |
---|
540 | _ARM_Data_synchronization_barrier(); |
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541 | _ARM_Send_event(); |
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542 | } |
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543 | |
---|
544 | static inline void _CPU_SMP_Processor_event_receive( void ) |
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545 | { |
---|
546 | _ARM_Wait_for_event(); |
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547 | _ARM_Data_memory_barrier(); |
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548 | } |
---|
549 | #endif |
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550 | |
---|
551 | |
---|
552 | static inline uint32_t CPU_swap_u32( uint32_t value ) |
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553 | { |
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554 | #if defined(__thumb2__) |
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555 | __asm__ volatile ( |
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556 | "rev %0, %0" |
---|
557 | : "=r" (value) |
---|
558 | : "0" (value) |
---|
559 | ); |
---|
560 | return value; |
---|
561 | #elif defined(__thumb__) |
---|
562 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
563 | |
---|
564 | byte4 = (value >> 24) & 0xff; |
---|
565 | byte3 = (value >> 16) & 0xff; |
---|
566 | byte2 = (value >> 8) & 0xff; |
---|
567 | byte1 = value & 0xff; |
---|
568 | |
---|
569 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
570 | return swapped; |
---|
571 | #else |
---|
572 | uint32_t tmp = value; /* make compiler warnings go away */ |
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573 | __asm__ volatile ("EOR %1, %0, %0, ROR #16\n" |
---|
574 | "BIC %1, %1, #0xff0000\n" |
---|
575 | "MOV %0, %0, ROR #8\n" |
---|
576 | "EOR %0, %0, %1, LSR #8\n" |
---|
577 | : "=r" (value), "=r" (tmp) |
---|
578 | : "0" (value), "1" (tmp)); |
---|
579 | return value; |
---|
580 | #endif |
---|
581 | } |
---|
582 | |
---|
583 | static inline uint16_t CPU_swap_u16( uint16_t value ) |
---|
584 | { |
---|
585 | #if defined(__thumb2__) |
---|
586 | __asm__ volatile ( |
---|
587 | "rev16 %0, %0" |
---|
588 | : "=r" (value) |
---|
589 | : "0" (value) |
---|
590 | ); |
---|
591 | return value; |
---|
592 | #else |
---|
593 | return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU)); |
---|
594 | #endif |
---|
595 | } |
---|
596 | |
---|
597 | typedef uint32_t CPU_Counter_ticks; |
---|
598 | |
---|
599 | CPU_Counter_ticks _CPU_Counter_read( void ); |
---|
600 | |
---|
601 | CPU_Counter_ticks _CPU_Counter_difference( |
---|
602 | CPU_Counter_ticks second, |
---|
603 | CPU_Counter_ticks first |
---|
604 | ); |
---|
605 | |
---|
606 | #if CPU_PROVIDES_IDLE_THREAD_BODY == TRUE |
---|
607 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
---|
608 | #endif |
---|
609 | |
---|
610 | /** @} */ |
---|
611 | |
---|
612 | /** |
---|
613 | * @addtogroup ScoreCPUARM |
---|
614 | */ |
---|
615 | /**@{**/ |
---|
616 | |
---|
617 | #if defined(ARM_MULTILIB_ARCH_V4) |
---|
618 | |
---|
619 | typedef enum { |
---|
620 | ARM_EXCEPTION_RESET = 0, |
---|
621 | ARM_EXCEPTION_UNDEF = 1, |
---|
622 | ARM_EXCEPTION_SWI = 2, |
---|
623 | ARM_EXCEPTION_PREF_ABORT = 3, |
---|
624 | ARM_EXCEPTION_DATA_ABORT = 4, |
---|
625 | ARM_EXCEPTION_RESERVED = 5, |
---|
626 | ARM_EXCEPTION_IRQ = 6, |
---|
627 | ARM_EXCEPTION_FIQ = 7, |
---|
628 | MAX_EXCEPTIONS = 8, |
---|
629 | ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff |
---|
630 | } Arm_symbolic_exception_name; |
---|
631 | |
---|
632 | #endif /* defined(ARM_MULTILIB_ARCH_V4) */ |
---|
633 | |
---|
634 | typedef struct { |
---|
635 | uint32_t register_fpexc; |
---|
636 | uint32_t register_fpscr; |
---|
637 | uint64_t register_d0; |
---|
638 | uint64_t register_d1; |
---|
639 | uint64_t register_d2; |
---|
640 | uint64_t register_d3; |
---|
641 | uint64_t register_d4; |
---|
642 | uint64_t register_d5; |
---|
643 | uint64_t register_d6; |
---|
644 | uint64_t register_d7; |
---|
645 | uint64_t register_d8; |
---|
646 | uint64_t register_d9; |
---|
647 | uint64_t register_d10; |
---|
648 | uint64_t register_d11; |
---|
649 | uint64_t register_d12; |
---|
650 | uint64_t register_d13; |
---|
651 | uint64_t register_d14; |
---|
652 | uint64_t register_d15; |
---|
653 | uint64_t register_d16; |
---|
654 | uint64_t register_d17; |
---|
655 | uint64_t register_d18; |
---|
656 | uint64_t register_d19; |
---|
657 | uint64_t register_d20; |
---|
658 | uint64_t register_d21; |
---|
659 | uint64_t register_d22; |
---|
660 | uint64_t register_d23; |
---|
661 | uint64_t register_d24; |
---|
662 | uint64_t register_d25; |
---|
663 | uint64_t register_d26; |
---|
664 | uint64_t register_d27; |
---|
665 | uint64_t register_d28; |
---|
666 | uint64_t register_d29; |
---|
667 | uint64_t register_d30; |
---|
668 | uint64_t register_d31; |
---|
669 | } ARM_VFP_context; |
---|
670 | |
---|
671 | typedef struct { |
---|
672 | uint32_t register_r0; |
---|
673 | uint32_t register_r1; |
---|
674 | uint32_t register_r2; |
---|
675 | uint32_t register_r3; |
---|
676 | uint32_t register_r4; |
---|
677 | uint32_t register_r5; |
---|
678 | uint32_t register_r6; |
---|
679 | uint32_t register_r7; |
---|
680 | uint32_t register_r8; |
---|
681 | uint32_t register_r9; |
---|
682 | uint32_t register_r10; |
---|
683 | uint32_t register_r11; |
---|
684 | uint32_t register_r12; |
---|
685 | uint32_t register_sp; |
---|
686 | void *register_lr; |
---|
687 | void *register_pc; |
---|
688 | #if defined(ARM_MULTILIB_ARCH_V4) |
---|
689 | uint32_t register_cpsr; |
---|
690 | Arm_symbolic_exception_name vector; |
---|
691 | #elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) |
---|
692 | uint32_t register_xpsr; |
---|
693 | uint32_t vector; |
---|
694 | #endif |
---|
695 | const ARM_VFP_context *vfp_context; |
---|
696 | uint32_t reserved_for_stack_alignment; |
---|
697 | } CPU_Exception_frame; |
---|
698 | |
---|
699 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
700 | |
---|
701 | void _ARM_Exception_default( CPU_Exception_frame *frame ); |
---|
702 | |
---|
703 | /** @} */ |
---|
704 | |
---|
705 | /** Type that can store a 32-bit integer or a pointer. */ |
---|
706 | typedef uintptr_t CPU_Uint32ptr; |
---|
707 | |
---|
708 | #ifdef __cplusplus |
---|
709 | } |
---|
710 | #endif |
---|
711 | |
---|
712 | #endif /* ASM */ |
---|
713 | |
---|
714 | #endif /* _RTEMS_SCORE_CPU_H */ |
---|