1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /* |
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4 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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5 | * |
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6 | * Redistribution and use in source and binary forms, with or without |
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7 | * modification, are permitted provided that the following conditions |
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8 | * are met: |
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9 | * 1. Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * 2. Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * |
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15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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17 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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18 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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19 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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20 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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21 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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22 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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23 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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24 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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25 | * POSSIBILITY OF SUCH DAMAGE. |
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26 | */ |
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27 | |
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28 | #ifndef RTEMS_SCORE_ARMV4_H |
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29 | #define RTEMS_SCORE_ARMV4_H |
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30 | |
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31 | #include <rtems/score/cpu.h> |
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32 | |
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33 | #ifdef __cplusplus |
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34 | extern "C" { |
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35 | #endif /* __cplusplus */ |
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36 | |
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37 | #ifdef ARM_MULTILIB_ARCH_V4 |
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38 | |
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39 | void bsp_interrupt_dispatch( void ); |
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40 | |
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41 | void _ARMV4_Exception_interrupt( void ); |
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42 | |
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43 | typedef void ARMV4_Exception_abort_handler( CPU_Exception_frame *frame ); |
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44 | |
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45 | void _ARMV4_Exception_data_abort_set_handler( |
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46 | ARMV4_Exception_abort_handler handler |
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47 | ); |
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48 | |
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49 | void _ARMV4_Exception_data_abort( void ); |
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50 | |
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51 | void _ARMV4_Exception_prefetch_abort_set_handler( |
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52 | ARMV4_Exception_abort_handler handler |
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53 | ); |
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54 | |
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55 | void _ARMV4_Exception_prefetch_abort( void ); |
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56 | |
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57 | void _ARMV4_Exception_undef_default( void ); |
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58 | |
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59 | void _ARMV4_Exception_swi_default( void ); |
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60 | |
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61 | void _ARMV4_Exception_data_abort_default( void ); |
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62 | |
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63 | void _ARMV4_Exception_pref_abort_default( void ); |
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64 | |
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65 | void _ARMV4_Exception_reserved_default( void ); |
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66 | |
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67 | void _ARMV4_Exception_irq_default( void ); |
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68 | |
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69 | void _ARMV4_Exception_fiq_default( void ); |
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70 | |
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71 | static inline uint32_t _ARMV4_Status_irq_enable( void ) |
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72 | { |
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73 | uint32_t arm_switch_reg; |
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74 | uint32_t psr; |
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75 | |
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76 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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77 | |
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78 | __asm__ volatile ( |
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79 | ARM_SWITCH_TO_ARM |
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80 | "mrs %[psr], cpsr\n" |
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81 | "bic %[arm_switch_reg], %[psr], #0x80\n" |
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82 | "msr cpsr, %[arm_switch_reg]\n" |
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83 | ARM_SWITCH_BACK |
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84 | : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr) |
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85 | ); |
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86 | |
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87 | return psr; |
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88 | } |
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89 | |
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90 | static inline void _ARMV4_Status_restore( uint32_t psr ) |
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91 | { |
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92 | ARM_SWITCH_REGISTERS; |
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93 | |
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94 | __asm__ volatile ( |
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95 | ARM_SWITCH_TO_ARM |
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96 | "msr cpsr, %[psr]\n" |
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97 | ARM_SWITCH_BACK |
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98 | : ARM_SWITCH_OUTPUT |
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99 | : [psr] "r" (psr) |
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100 | ); |
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101 | |
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102 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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103 | } |
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104 | |
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105 | #endif /* ARM_MULTILIB_ARCH_V4 */ |
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106 | |
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107 | #ifdef __cplusplus |
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108 | } |
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109 | #endif /* __cplusplus */ |
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110 | |
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111 | #endif /* RTEMS_SCORE_ARMV4_H */ |
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