source: rtems/cpukit/score/cpu/arm/include/rtems/score/armv4.h @ 255fe43

Last change on this file since 255fe43 was 255fe43, checked in by Joel Sherrill <joel@…>, on 03/01/22 at 20:40:44

cpukit/: Scripted embedded brains header file clean up

Updates #4625.

  • Property mode set to 100644
File size: 3.1 KB
Line 
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#ifndef RTEMS_SCORE_ARMV4_H
29#define RTEMS_SCORE_ARMV4_H
30
31#include <rtems/score/cpu.h>
32
33#ifdef __cplusplus
34extern "C" {
35#endif /* __cplusplus */
36
37#ifdef ARM_MULTILIB_ARCH_V4
38
39void bsp_interrupt_dispatch( void );
40
41void _ARMV4_Exception_interrupt( void );
42
43typedef void ARMV4_Exception_abort_handler( CPU_Exception_frame *frame );
44
45void _ARMV4_Exception_data_abort_set_handler(
46  ARMV4_Exception_abort_handler handler
47);
48
49void _ARMV4_Exception_data_abort( void );
50
51void _ARMV4_Exception_prefetch_abort_set_handler(
52  ARMV4_Exception_abort_handler handler
53);
54
55void _ARMV4_Exception_prefetch_abort( void );
56
57void _ARMV4_Exception_undef_default( void );
58
59void _ARMV4_Exception_swi_default( void );
60
61void _ARMV4_Exception_data_abort_default( void );
62
63void _ARMV4_Exception_pref_abort_default( void );
64
65void _ARMV4_Exception_reserved_default( void );
66
67void _ARMV4_Exception_irq_default( void );
68
69void _ARMV4_Exception_fiq_default( void );
70
71static inline uint32_t _ARMV4_Status_irq_enable( void )
72{
73  uint32_t arm_switch_reg;
74  uint32_t psr;
75
76  RTEMS_COMPILER_MEMORY_BARRIER();
77
78  __asm__ volatile (
79    ARM_SWITCH_TO_ARM
80    "mrs %[psr], cpsr\n"
81    "bic %[arm_switch_reg], %[psr], #0x80\n"
82    "msr cpsr, %[arm_switch_reg]\n"
83    ARM_SWITCH_BACK
84    : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr)
85  );
86
87  return psr;
88}
89
90static inline void _ARMV4_Status_restore( uint32_t psr )
91{
92  ARM_SWITCH_REGISTERS;
93
94  __asm__ volatile (
95    ARM_SWITCH_TO_ARM
96    "msr cpsr, %[psr]\n"
97    ARM_SWITCH_BACK
98    : ARM_SWITCH_OUTPUT
99    : [psr] "r" (psr)
100  );
101
102  RTEMS_COMPILER_MEMORY_BARRIER();
103}
104
105#endif /* ARM_MULTILIB_ARCH_V4 */
106
107#ifdef __cplusplus
108}
109#endif /* __cplusplus */
110
111#endif /* RTEMS_SCORE_ARMV4_H */
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