1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @ingroup RTEMSScoreCPUARMPMSAv8 |
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7 | * |
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8 | * @brief This header file provides the API to manage an Arm PMSAv8-32 based |
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9 | * Memory Protection Unit (MPU). |
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10 | */ |
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11 | |
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12 | /* |
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13 | * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions |
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17 | * are met: |
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18 | * 1. Redistributions of source code must retain the above copyright |
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19 | * notice, this list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright |
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21 | * notice, this list of conditions and the following disclaimer in the |
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22 | * documentation and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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34 | * POSSIBILITY OF SUCH DAMAGE. |
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35 | */ |
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36 | |
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37 | #ifndef _RTEMS_SCORE_AARCH32_PMSA_H |
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38 | #define _RTEMS_SCORE_AARCH32_PMSA_H |
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39 | |
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40 | #include <stddef.h> |
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41 | #include <stdint.h> |
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42 | |
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43 | #ifdef __cplusplus |
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44 | extern "C" { |
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45 | #endif |
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46 | |
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47 | /** |
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48 | * @defgroup RTEMSScoreCPUARMPMSAv8 PMSAv8-32 Support |
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49 | * |
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50 | * @ingroup RTEMSScoreCPUARM |
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51 | * |
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52 | * @brief This group provides support functions to manage an Arm PMSAv8-32 |
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53 | * (Protected Memory System Architecture) based Memory Protection Unit (MPU). |
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54 | * |
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55 | * @{ |
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56 | */ |
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57 | |
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58 | #define AARCH32_PMSA_MIN_REGION_ALIGN 64 |
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59 | |
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60 | #define AARCH32_PMSA_ATTR_EN 0x1U |
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61 | |
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62 | #define AARCH32_PMSA_ATTR_IDX_SHIFT 1 |
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63 | #define AARCH32_PMSA_ATTR_IDX_MASK 0xeU |
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64 | #define AARCH32_PMSA_ATTR_IDX( _idx ) \ |
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65 | ( ( _idx ) << AARCH32_PMSA_ATTR_IDX_SHIFT ) |
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66 | |
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67 | #define AARCH32_PMSA_ATTR_XN 0x6U |
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68 | |
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69 | #define AARCH32_PMSA_ATTR_AP_SHIFT 7 |
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70 | #define AARCH32_PMSA_ATTR_AP_MASK 0x18U |
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71 | #define AARCH32_PMSA_ATTR_AP( _ap ) \ |
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72 | ( ( _ap ) << AARCH32_PMSA_ATTR_AP_SHIFT ) |
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73 | #define AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO 0x0U |
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74 | #define AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_RW 0x1U |
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75 | #define AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_NO 0x2U |
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76 | #define AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_RO 0x3U |
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77 | |
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78 | #define AARCH32_PMSA_ATTR_SH_SHIFT 9 |
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79 | #define AARCH32_PMSA_ATTR_SH_MASK 0x600U |
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80 | #define AARCH32_PMSA_ATTR_SH( _sh ) \ |
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81 | ( ( _sh ) << AARCH32_PMSA_ATTR_SH_SHIFT ) |
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82 | #define AARCH32_PMSA_ATTR_SH_NO 0x0U |
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83 | #define AARCH32_PMSA_ATTR_SH_RES 0x1U |
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84 | #define AARCH32_PMSA_ATTR_SH_OUTER 0x2U |
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85 | #define AARCH32_PMSA_ATTR_SH_INNER 0x3U |
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86 | |
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87 | #define AARCH32_PMSA_MEM_DEVICE_NG_NR_NE 0x00U |
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88 | #define AARCH32_PMSA_MEM_DEVICE_NG_NR_E 0x04U |
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89 | #define AARCH32_PMSA_MEM_DEVICE_NG_R_E 0x08U |
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90 | #define AARCH32_PMSA_MEM_DEVICE_G_R_E 0x0cU |
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91 | |
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92 | #define AARCH32_PMSA_MEM_OUTER_WTT 0x00U |
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93 | #define AARCH32_PMSA_MEM_OUTER_NC 0x40U |
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94 | #define AARCH32_PMSA_MEM_OUTER_WBT 0x40U |
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95 | #define AARCH32_PMSA_MEM_OUTER_WTNT 0x80U |
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96 | #define AARCH32_PMSA_MEM_OUTER_WBNT 0xc0U |
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97 | |
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98 | #define AARCH32_PMSA_MEM_OUTER_RA 0x20U |
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99 | #define AARCH32_PMSA_MEM_OUTER_WA 0x10U |
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100 | |
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101 | #define AARCH32_PMSA_MEM_INNER_WTT 0x00U |
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102 | #define AARCH32_PMSA_MEM_INNER_NC 0x40U |
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103 | #define AARCH32_PMSA_MEM_INNER_WBT 0x40U |
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104 | #define AARCH32_PMSA_MEM_INNER_WTNT 0x80U |
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105 | #define AARCH32_PMSA_MEM_INNER_WBNT 0xc0U |
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106 | |
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107 | #define AARCH32_PMSA_MEM_INNER_RA 0x02U |
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108 | #define AARCH32_PMSA_MEM_INNER_WA 0x01U |
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109 | |
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110 | #define AARCH32_PMSA_MEM_ATTR( _ma0, _ma1, _ma2, _ma3 ) \ |
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111 | ( ( _ma0 ) | ( ( _ma1 ) << 8 ) | ( ( _ma1 ) << 16 ) | ( ( _ma1 ) << 24 ) ) |
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112 | |
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113 | #define AARCH32_PMSA_MEM_ATTR_DEFAULT_CACHED \ |
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114 | ( AARCH32_PMSA_MEM_OUTER_WBNT | \ |
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115 | AARCH32_PMSA_MEM_OUTER_RA | \ |
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116 | AARCH32_PMSA_MEM_OUTER_WA | \ |
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117 | AARCH32_PMSA_MEM_INNER_WBNT | \ |
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118 | AARCH32_PMSA_MEM_INNER_RA | \ |
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119 | AARCH32_PMSA_MEM_INNER_WA ) |
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120 | |
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121 | #define AARCH32_PMSA_MEM_ATTR_DEFAULT_UNCACHED \ |
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122 | ( AARCH32_PMSA_MEM_OUTER_NC | \ |
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123 | AARCH32_PMSA_MEM_INNER_NC ) |
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124 | |
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125 | #define AARCH32_PMSA_MEM_ATTR_DEFAULT_DEVICE \ |
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126 | AARCH32_PMSA_MEM_DEVICE_NG_NR_NE |
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127 | |
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128 | #define AARCH32_PMSA_CODE_CACHED \ |
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129 | ( AARCH32_PMSA_ATTR_EN | \ |
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130 | AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_NO ) | \ |
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131 | AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \ |
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132 | AARCH32_PMSA_ATTR_IDX( 0U ) ) |
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133 | |
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134 | #define AARCH32_PMSA_CODE_UNCACHED \ |
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135 | ( AARCH32_PMSA_ATTR_EN | \ |
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136 | AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_NO ) | \ |
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137 | AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \ |
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138 | AARCH32_PMSA_ATTR_IDX( 1U ) ) |
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139 | |
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140 | #define AARCH32_PMSA_DATA_READ_ONLY_CACHED \ |
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141 | ( AARCH32_PMSA_ATTR_EN | \ |
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142 | AARCH32_PMSA_ATTR_XN | \ |
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143 | AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_NO ) | \ |
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144 | AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_OUTER ) | \ |
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145 | AARCH32_PMSA_ATTR_IDX( 0U ) ) |
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146 | |
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147 | #define AARCH32_PMSA_DATA_READ_ONLY_UNCACHED \ |
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148 | ( AARCH32_PMSA_ATTR_EN | \ |
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149 | AARCH32_PMSA_ATTR_XN | \ |
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150 | AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_NO ) | \ |
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151 | AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \ |
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152 | AARCH32_PMSA_ATTR_IDX( 1U ) ) |
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153 | |
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154 | #define AARCH32_PMSA_DATA_READ_WRITE_CACHED \ |
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155 | ( AARCH32_PMSA_ATTR_EN | \ |
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156 | AARCH32_PMSA_ATTR_XN | \ |
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157 | AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO | \ |
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158 | AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_OUTER ) | \ |
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159 | AARCH32_PMSA_ATTR_IDX( 0U ) ) |
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160 | |
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161 | #define AARCH32_PMSA_DATA_READ_WRITE_UNCACHED \ |
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162 | ( AARCH32_PMSA_ATTR_EN | \ |
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163 | AARCH32_PMSA_ATTR_XN | \ |
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164 | AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO ) | \ |
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165 | AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \ |
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166 | AARCH32_PMSA_ATTR_IDX( 1U ) ) |
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167 | |
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168 | #define AARCH32_PMSA_DEVICE \ |
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169 | ( AARCH32_PMSA_ATTR_EN | \ |
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170 | AARCH32_PMSA_ATTR_XN | \ |
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171 | AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO ) | \ |
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172 | AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \ |
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173 | AARCH32_PMSA_ATTR_IDX( 2U ) ) |
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174 | |
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175 | /** |
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176 | * @brief The default section definitions shall be used by the BSP to define |
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177 | * ::_AArch32_PMSA_Sections. |
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178 | * |
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179 | * In addition to the default section definitions, the BSP should provide |
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180 | * section definitions for the memory-mapped devices and other memory areas. |
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181 | */ |
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182 | #define AARCH32_PMSA_DEFAULT_SECTIONS \ |
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183 | { \ |
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184 | .begin = (uint32_t) bsp_section_fast_text_begin, \ |
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185 | .end = (uint32_t) bsp_section_fast_text_end, \ |
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186 | .attributes = AARCH32_PMSA_CODE_CACHED \ |
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187 | }, { \ |
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188 | .begin = (uint32_t) bsp_section_fast_data_begin, \ |
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189 | .end = (uint32_t) bsp_section_fast_data_end, \ |
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190 | .attributes = AARCH32_PMSA_DATA_READ_WRITE_CACHED \ |
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191 | }, { \ |
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192 | .begin = (uint32_t) bsp_section_start_begin, \ |
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193 | .end = (uint32_t) bsp_section_start_end, \ |
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194 | .attributes = AARCH32_PMSA_CODE_CACHED \ |
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195 | }, { \ |
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196 | .begin = (uint32_t) bsp_section_vector_begin, \ |
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197 | .end = (uint32_t) bsp_section_vector_end, \ |
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198 | .attributes = AARCH32_PMSA_CODE_CACHED \ |
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199 | }, { \ |
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200 | .begin = (uint32_t) bsp_section_text_begin, \ |
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201 | .end = (uint32_t) bsp_section_text_end, \ |
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202 | .attributes = AARCH32_PMSA_CODE_CACHED \ |
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203 | }, { \ |
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204 | .begin = (uint32_t) bsp_section_rodata_begin, \ |
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205 | .end = (uint32_t) bsp_section_rodata_end, \ |
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206 | .attributes = AARCH32_PMSA_DATA_READ_ONLY_CACHED \ |
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207 | }, { \ |
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208 | .begin = (uint32_t) bsp_section_data_begin, \ |
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209 | .end = (uint32_t) bsp_section_data_end, \ |
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210 | .attributes = AARCH32_PMSA_DATA_READ_WRITE_CACHED \ |
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211 | }, { \ |
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212 | .begin = (uint32_t) bsp_section_bss_begin, \ |
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213 | .end = (uint32_t) bsp_section_bss_end, \ |
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214 | .attributes = AARCH32_PMSA_DATA_READ_WRITE_CACHED \ |
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215 | }, { \ |
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216 | .begin = (uint32_t) bsp_section_rtemsstack_begin, \ |
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217 | .end = (uint32_t) bsp_section_rtemsstack_end, \ |
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218 | .attributes = AARCH32_PMSA_DATA_READ_WRITE_CACHED \ |
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219 | }, { \ |
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220 | .begin = (uint32_t) bsp_section_work_begin, \ |
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221 | .end = (uint32_t) bsp_section_work_end, \ |
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222 | .attributes = AARCH32_PMSA_DATA_READ_WRITE_CACHED \ |
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223 | }, { \ |
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224 | .begin = (uint32_t) bsp_section_stack_begin, \ |
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225 | .end = (uint32_t) bsp_section_stack_end, \ |
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226 | .attributes = AARCH32_PMSA_DATA_READ_WRITE_CACHED \ |
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227 | }, { \ |
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228 | .begin = (uint32_t) bsp_section_nocache_begin, \ |
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229 | .end = (uint32_t) bsp_section_nocache_end, \ |
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230 | .attributes = AARCH32_PMSA_DATA_READ_WRITE_UNCACHED \ |
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231 | }, { \ |
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232 | .begin = (uint32_t) bsp_section_nocachenoload_begin, \ |
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233 | .end = (uint32_t) bsp_section_nocachenoload_end, \ |
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234 | .attributes = AARCH32_PMSA_DATA_READ_WRITE_UNCACHED \ |
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235 | } |
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236 | |
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237 | /** |
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238 | * @brief The section definition is used to initialize the Memory Protection |
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239 | * Unit (MPU). |
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240 | * |
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241 | * A section is empty if the begin address is equal to the end address. |
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242 | */ |
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243 | typedef struct { |
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244 | /** |
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245 | * @brief This member defines the begin address of the section. |
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246 | */ |
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247 | uint32_t begin; |
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248 | |
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249 | /** |
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250 | * @brief This member defines the end address of the section. |
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251 | */ |
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252 | uint32_t end; |
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253 | |
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254 | /** |
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255 | * @brief This member defines the attributes of the section. |
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256 | */ |
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257 | uint32_t attributes; |
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258 | } AArch32_PMSA_Section; |
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259 | |
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260 | /** |
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261 | * @brief Initializes the Memory Protection Unit (MPU). |
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262 | * |
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263 | * The section definitions are used to define the regions of the MPU. Sections |
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264 | * are merged if possible to reduce the count of used regions. If too many |
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265 | * regions are used, then the MPU is not enabled. Overlapping section |
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266 | * definitions result in undefined system behaviour. |
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267 | * |
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268 | * @param memory_attributes_0 are the memory attributes for MAIR0. |
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269 | * |
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270 | * @param memory_attributes_1 are the memory attributes for MAIR1. |
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271 | * |
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272 | * @param sections is the array with section definitions. |
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273 | * |
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274 | * @param section_count is the count of section definitions. |
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275 | */ |
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276 | void _AArch32_PMSA_Initialize( |
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277 | uint32_t memory_attributes_0, |
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278 | uint32_t memory_attributes_1, |
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279 | const AArch32_PMSA_Section *sections, |
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280 | size_t section_count |
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281 | ); |
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282 | |
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283 | /** |
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284 | * @brief This array provides section definitions to initialize the memory |
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285 | * protection unit (MPU). |
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286 | * |
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287 | * The BSP shall provide the section definitions with the help of |
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288 | * ::AARCH32_PMSA_DEFAULT_SECTIONS. The section count is provided by |
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289 | * ::_AArch32_PMSA_Section_count. |
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290 | */ |
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291 | extern const AArch32_PMSA_Section _AArch32_PMSA_Sections[]; |
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292 | |
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293 | /** |
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294 | * @brief This constant provides the count of elements in |
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295 | * ::_AArch32_PMSA_Sections. |
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296 | */ |
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297 | extern const size_t _AArch32_PMSA_Section_count; |
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298 | |
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299 | /** |
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300 | * @brief Initializes the Memory Protection Unit (MPU) using the section |
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301 | * definitions with default memory attributes. |
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302 | * |
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303 | * Calls _AArch32_PMSA_Initialize() using ::_AArch32_PMSA_Sections and |
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304 | * ::_AArch32_PMSA_Section_count and the default memory attributes. |
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305 | */ |
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306 | void _AArch32_PMSA_Initialize_default( void ); |
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307 | |
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308 | /** @} */ |
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309 | |
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310 | #ifdef __cplusplus |
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311 | } |
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312 | #endif |
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313 | |
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314 | #endif /* _RTEMS_SCORE_AARCH32_PMSA_H */ |
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