1 | /* |
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2 | * $Id$ |
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3 | * |
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4 | * This file contains all assembly code for the ARM implementation |
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5 | * of RTEMS. |
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6 | * |
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7 | * Copyright (c) 2002 by Advent Networks, Inc. |
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8 | * Jay Monkman <jmonkman@adventnetworks.com> |
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9 | * |
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10 | * COPYRIGHT (c) 2000 Canon Research Centre France SA. |
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11 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.com/license/LICENSE. |
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16 | * |
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17 | */ |
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18 | |
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19 | #include <asm.h> |
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20 | #include <rtems/score/cpu_asm.h> |
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21 | |
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22 | |
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23 | /* |
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24 | * void _CPU_Context_switch( run_context, heir_context ) |
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25 | * void _CPU_Context_restore( run_context, heir_context ) |
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26 | * |
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27 | * This routine performs a normal non-FP context. |
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28 | * |
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29 | * R0 = run_context R1 = heir_context |
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30 | * |
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31 | * This function copies the current registers to where r0 points, then |
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32 | * restores the ones from where r1 points. |
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33 | * |
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34 | * Using the ldm/stm opcodes save 2-3 us on 100 MHz ARM9TDMI with |
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35 | * a 16 bit data bus. |
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36 | * |
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37 | */ |
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38 | .globl _CPU_Context_switch |
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39 | _CPU_Context_switch: |
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40 | /* Start saving context */ |
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41 | mrs r2, cpsr |
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42 | stmia r0, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14} |
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43 | |
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44 | |
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45 | /* Start restoring context */ |
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46 | _restore: |
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47 | ldmia r1, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14} |
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48 | msr cpsr, r2 |
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49 | mov pc, lr |
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50 | |
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51 | /* |
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52 | * void _CPU_Context_restore( new_context ) |
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53 | * |
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54 | * This function copies the restores the registers from where r0 points. |
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55 | * It must match _CPU_Context_switch() |
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56 | * |
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57 | */ |
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58 | .globl _CPU_Context_restore |
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59 | _CPU_Context_restore: |
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60 | mov r1, r0 |
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61 | b _restore |
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62 | |
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63 | |
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64 | |
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65 | /* FIXME: _Exception_Handler_Undef_Swi is untested */ |
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66 | .globl _Exception_Handler_Undef_Swi |
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67 | _Exception_Handler_Undef_Swi: |
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68 | /* FIXME: This should use load and store multiple instructions */ |
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69 | sub r13,r13,#SIZE_REGS |
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70 | str r4, [r13, #REG_R4] |
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71 | str r5, [r13, #REG_R5] |
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72 | str r6, [r13, #REG_R6] |
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73 | str r7, [r13, #REG_R7] |
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74 | str r8, [r13, #REG_R8] |
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75 | str r9, [r13, #REG_R9] |
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76 | str r10, [r13, #REG_R10] |
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77 | str r11, [r13, #REG_R11] |
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78 | str sp, [r13, #REG_SP] |
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79 | str lr, [r13, #REG_LR] |
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80 | mrs r0, cpsr /* read the status */ |
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81 | and r0, r0,#0x1f /* we keep the mode as exception number */ |
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82 | str r0, [r13, #REG_PC] /* we store it in a free place */ |
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83 | mov r0, r13 /* put frame address in r0 (C arg 1) */ |
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84 | |
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85 | ldr r1, =SWI_Handler |
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86 | ldr lr, =_go_back_1 |
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87 | ldr pc,[r1] /* call handler */ |
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88 | _go_back_1: |
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89 | ldr r4, [r13, #REG_R4] |
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90 | ldr r5, [r13, #REG_R5] |
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91 | ldr r6, [r13, #REG_R6] |
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92 | ldr r7, [r13, #REG_R7] |
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93 | ldr r8, [r13, #REG_R8] |
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94 | ldr r9, [r13, #REG_R9] |
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95 | ldr r10, [r13, #REG_R10] |
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96 | ldr r11, [r13, #REG_R11] |
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97 | ldr sp, [r13, #REG_SP] |
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98 | ldr lr, [r13, #REG_LR] |
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99 | add r13,r13,#SIZE_REGS |
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100 | movs pc,r14 /* return */ |
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101 | |
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102 | /* FIXME: _Exception_Handler_Abort is untested */ |
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103 | .globl _Exception_Handler_Abort |
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104 | _Exception_Handler_Abort: |
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105 | /* FIXME: This should use load and store multiple instructions */ |
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106 | sub r13,r13,#SIZE_REGS |
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107 | str r4, [r13, #REG_R4] |
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108 | str r5, [r13, #REG_R5] |
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109 | str r6, [r13, #REG_R6] |
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110 | str r7, [r13, #REG_R7] |
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111 | str r8, [r13, #REG_R8] |
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112 | str r9, [r13, #REG_R9] |
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113 | str sp, [r13, #REG_R11] |
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114 | str lr, [r13, #REG_SP] |
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115 | str lr, [r13, #REG_LR] |
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116 | mrs r0, cpsr /* read the status */ |
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117 | and r0, r0,#0x1f /* we keep the mode as exception number */ |
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118 | str r0, [r13, #REG_PC] /* we store it in a free place */ |
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119 | mov r0, r13 /* put frame address in ro (C arg 1) */ |
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120 | |
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121 | ldr r1, =_currentExcHandler |
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122 | ldr lr, =_go_back_2 |
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123 | ldr pc,[r1] /* call handler */ |
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124 | _go_back_2: |
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125 | ldr r4, [r13, #REG_R4] |
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126 | ldr r5, [r13, #REG_R5] |
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127 | ldr r6, [r13, #REG_R6] |
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128 | ldr r7, [r13, #REG_R7] |
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129 | ldr r8, [r13, #REG_R8] |
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130 | ldr r9, [r13, #REG_R9] |
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131 | ldr r10, [r13, #REG_R10] |
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132 | ldr sp, [r13, #REG_R11] |
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133 | ldr lr, [r13, #REG_SP] |
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134 | ldr lr, [r13, #REG_LR] |
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135 | add r13,r13,#SIZE_REGS |
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136 | subs pc,r14,#4 /* return */ |
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137 | |
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138 | .globl _exc_data_abort |
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139 | _exc_data_abort: |
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140 | sub sp, sp, #SIZE_REGS /* reserve register frame */ |
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141 | stmia sp, {r0-r12} |
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142 | str lr, [sp, #REG_LR] |
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143 | mov r1, lr |
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144 | ldr r0, [r1, #-8] /* r0 = bad instruction */ |
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145 | mrs r1, spsr /* r1 = spsr */ |
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146 | mov r2, r13 /* r2 = exception frame */ |
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147 | bl do_data_abort |
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148 | |
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149 | ldr lr, [sp, #REG_LR] |
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150 | ldmia sp, {r0-r12} |
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151 | add sp, sp, #SIZE_REGS |
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152 | |
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153 | subs pc, r14, #4 /* return to the instruction */ |
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154 | /* _AFTER_ the aborted one */ |
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