source: rtems/cpukit/score/cpu/arm/cpu_asm.S @ 4f0b287

4.104.114.84.95
Last change on this file since 4f0b287 was 4f0b287, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 17, 2002 at 5:14:31 PM

2002-07-17 Jay Monkman <jtm@…>

  • rtems/score/cpu_asm.h: Enhanced to include register offsets.
  • Makefile.am: Install rtems/score/cpu_asm.h.
  • cpu.c: Significantly enhanced including the implementation of _CPU_ISR_Get_level.
  • cpu_asm.S: Improved behavior of context switch and interrupt dispatching.
  • rtems/score/arm.h: Improved the CPU model name determination.
  • rtems/score/cpu.h: Improved interrupt disable/enable functions.
  • Property mode set to 100644
File size: 6.0 KB
Line 
1/*
2 *  $Id$
3 *
4 *  This file contains all assembly code for the ARM implementation
5 *  of RTEMS.
6 *
7 *  Copyright (c) 2002 by Advent Networks, Inc.
8 *          Jay Monkman <jmonkman@adventnetworks.com>
9 *
10 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
11 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.OARcorp.com/rtems/license.html.
16 *
17 */
18
19#include <asm.h>
20#include <rtems/score/cpu_asm.h>
21
22
23/*
24 *  void _CPU_Context_switch( run_context, heir_context )
25 *  void _CPU_Context_restore( run_context, heir_context )
26 *
27 *  This routine performs a normal non-FP context.
28 *
29 *  R0 = run_context    R1 = heir_context
30 *
31 *  This function copies the current registers to where r0 points, then
32 *  restores the ones from where r1 points.
33 *
34 *
35 *  NOTE:  The function should be able to only save/restore the registers
36 *         that would be saved by a C function since the others have already
37 *         been saved.
38 *       
39 *         It should also be able to use the stm/ldm instructions.
40 *       
41 */
42
43        .globl _CPU_Context_switch
44_CPU_Context_switch:
45/* FIXME: This should use load and store multiple instructions */
46/* Start saving context */
47        str     r2,  [r0, #REG_R2]
48        str     r3,  [r0, #REG_R3]
49        str     r4,  [r0, #REG_R4]
50        str     r5,  [r0, #REG_R5]
51        str     r6,  [r0, #REG_R6]
52        str     r7,  [r0, #REG_R7]
53        str     r8,  [r0, #REG_R8]
54        str     r9,  [r0, #REG_R9]
55        str     r10, [r0, #REG_R10]
56       
57        str     r11, [r0, #REG_R11]
58        str     r12, [r0, #REG_R12]     
59       
60        str     sp,  [r0, #REG_SP]
61        str     lr,  [r0, #REG_PC]     /* save LR at PC's location */
62       
63        mrs     r2, cpsr
64        str     r2,  [r0, #REG_CPSR]
65
66/* Start restoring context */
67       
68        ldr     r2,  [r1, #REG_CPSR]
69        msr     cpsr, r2
70
71        ldr     r2,  [r1, #REG_R2]
72        ldr     r3,  [r1, #REG_R3]
73        ldr     r4,  [r1, #REG_R4]
74        ldr     r5,  [r1, #REG_R5]
75        ldr     r6,  [r1, #REG_R6]
76        ldr     r7,  [r1, #REG_R7]
77        ldr     r8,  [r1, #REG_R8]
78        ldr     r9,  [r1, #REG_R9]
79        ldr     r10, [r1, #REG_R10]     
80        ldr     r11, [r1, #REG_R11]
81        ldr     r12, [r1, #REG_R12]     
82       
83        ldr     sp,  [r1, #REG_SP]
84        ldr     lr,  [r1, #REG_PC]     
85        mov     pc, lr
86
87/*
88 *  void _CPU_Context_restore( new_context )
89 *
90 *  This function copies the restores the registers from where r0 points.
91 *  It must match _CPU_Context_switch()
92 *
93 *  NOTE:  The function should be able to only save/restore the registers
94 *         that would be saved by a C function since the others have already
95 *         been saved.
96 *       
97 *         It should also be able to use the stm/ldm instructions.
98 *       
99 */
100        .globl _CPU_Context_restore
101_CPU_Context_restore:
102/* FIXME: This should use load and store multiple instructions */
103        ldr     r2,  [r0, #REG_CPSR]
104        msr     cpsr, r2
105
106        ldr     r2,  [r0, #REG_R2]     
107        ldr     r3,  [r0, #REG_R3]
108        ldr     r4,  [r0, #REG_R4]
109        ldr     r5,  [r0, #REG_R5]
110        ldr     r6,  [r0, #REG_R6]
111        ldr     r7,  [r0, #REG_R7]
112        ldr     r8,  [r0, #REG_R8]
113        ldr     r9,  [r0, #REG_R9]
114        ldr     r10, [r0, #REG_R10]     
115        ldr     r11, [r1, #REG_R11]
116        ldr     r12, [r1, #REG_R12]     
117                       
118        ldr     sp,  [r0, #REG_SP]
119        ldr     lr,  [r0, #REG_PC]
120        mov     pc,  lr
121
122
123/* FIXME:       _Exception_Handler_Undef_Swi is untested */
124        .globl _Exception_Handler_Undef_Swi
125_Exception_Handler_Undef_Swi:
126/* FIXME: This should use load and store multiple instructions */
127        sub     r13,r13,#SIZE_REGS
128        str     r0,  [r13, #REG_R0]
129        str     r1,  [r13, #REG_R1]
130        str     r2,  [r13, #REG_R2]
131        str     r3,  [r13, #REG_R3]
132        str     r4,  [r13, #REG_R4]
133        str     r5,  [r13, #REG_R5]
134        str     r6,  [r13, #REG_R6]
135        str     r7,  [r13, #REG_R7]
136        str     r8,  [r13, #REG_R8]
137        str     r9,  [r13, #REG_R9]
138        str     r10, [r13, #REG_R10]
139        str     r11, [r13, #REG_R11]
140        str     r12, [r13, #REG_R12]
141        str     sp,  [r13, #REG_SP]
142        str     lr,  [r13, #REG_LR]
143        mrs     r0,  cpsr               /* read the status */
144        and     r0,  r0,#0x1f           /* we keep the mode as exception number */
145        str     r0,  [r13, #REG_PC]     /* we store it in a free place */
146        mov     r0,  r13                /* put frame address in r0 (C arg 1) */
147
148        ldr     r1, =SWI_Handler
149        ldr     lr, =_go_back_1
150        ldr     pc,[r1]                         /* call handler  */
151_go_back_1:
152        ldr     r0,  [r13, #REG_R0]
153        ldr     r1,  [r13, #REG_R1]
154        ldr     r2,  [r13, #REG_R2]
155        ldr     r3,  [r13, #REG_R3]
156        ldr     r4,  [r13, #REG_R4]
157        ldr     r5,  [r13, #REG_R5]
158        ldr     r6,  [r13, #REG_R6]
159        ldr     r7,  [r13, #REG_R7]
160        ldr     r8,  [r13, #REG_R8]
161        ldr     r9,  [r13, #REG_R9]
162        ldr     r10, [r13, #REG_R10]
163        ldr     r11, [r13, #REG_R11]
164        ldr     r12, [r13, #REG_R12]
165        ldr     sp,  [r13, #REG_SP]
166        ldr     lr,  [r13, #REG_LR]
167        add     r13,r13,#SIZE_REGS
168        movs    pc,r14                  /* return  */
169       
170/* FIXME:       _Exception_Handler_Abort is untested */
171        .globl _Exception_Handler_Abort
172_Exception_Handler_Abort:
173/* FIXME: This should use load and store multiple instructions */
174        sub     r13,r13,#SIZE_REGS
175        str     r0,  [r13, #REG_R0]
176        str     r1,  [r13, #REG_R1]
177        str     r2,  [r13, #REG_R2]
178        str     r3,  [r13, #REG_R3]
179        str     r4,  [r13, #REG_R4]
180        str     r5,  [r13, #REG_R5]
181        str     r6,  [r13, #REG_R6]
182        str     r7,  [r13, #REG_R7]
183        str     r8,  [r13, #REG_R8]
184        str     r9,  [r13, #REG_R9]
185        str     r10, [r13, #REG_R10]
186        str     sp,  [r13, #REG_R11]
187        str     lr,  [r13, #REG_R12]
188        str     lr,  [r13, #REG_SP]
189        str     lr,  [r13, #REG_LR]
190        mrs     r0,  cpsr               /* read the status */
191        and     r0,  r0,#0x1f           /* we keep the mode as exception number */
192        str     r0,  [r13, #REG_PC]     /* we store it in a free place */
193        mov     r0,  r13                /* put frame address in ro (C arg 1) */
194       
195        ldr     r1, =_currentExcHandler
196        ldr     lr, =_go_back_2
197        ldr     pc,[r1]                         /* call handler  */
198_go_back_2:
199        ldr     r0,  [r13, #REG_R0]
200        ldr     r1,  [r13, #REG_R1]
201        ldr     r2,  [r13, #REG_R2]
202        ldr     r3,  [r13, #REG_R3]
203        ldr     r4,  [r13, #REG_R4]
204        ldr     r5,  [r13, #REG_R5]
205        ldr     r6,  [r13, #REG_R6]
206        ldr     r7,  [r13, #REG_R7]
207        ldr     r8,  [r13, #REG_R8]
208        ldr     r9,  [r13, #REG_R9]
209        ldr     r10, [r13, #REG_R10]
210        ldr     sp,  [r13, #REG_R11]
211        ldr     lr,  [r13, #REG_R12]
212        ldr     lr,  [r13, #REG_SP]
213        ldr     lr,  [r13, #REG_LR]
214        add     r13,r13,#SIZE_REGS
215        subs    pc,r14,#4                       /* return */
216       
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