source: rtems/cpukit/score/cpu/arm/cpu.c @ cfd8d7a

4.115
Last change on this file since cfd8d7a was cfd8d7a, checked in by Sebastian Huber <sebastian.huber@…>, on May 8, 2013 at 7:30:31 AM

arm: Support VFP-D32 and Neon

  • Property mode set to 100644
File size: 3.4 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup ScoreCPU
5 *
6 * @brief ARM architecture support implementation.
7 */
8
9/*
10 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
11 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
12 *
13 *  Copyright (c) 2002 Advent Networks, Inc
14 *      Jay Monkman <jmonkman@adventnetworks.com>
15 *
16 *  Copyright (c) 2007 Ray xu <rayx.cn@gmail.com>
17 *
18 *  Copyright (c) 2009-2011 embedded brains GmbH
19 *
20 *  The license and distribution terms for this file may be
21 *  found in the file LICENSE in this distribution or at
22 *  http://www.rtems.com/license/LICENSE.
23 */
24
25#ifdef HAVE_CONFIG_H
26#include "config.h"
27#endif
28
29#include <rtems/system.h>
30#include <rtems.h>
31#include <rtems/bspIo.h>
32#include <rtems/score/isr.h>
33#include <rtems/score/wkspace.h>
34#include <rtems/score/thread.h>
35#include <rtems/score/cpu.h>
36
37#ifdef ARM_MULTILIB_VFP_D32
38  RTEMS_STATIC_ASSERT(
39    offsetof( Context_Control, register_d8 ) == ARM_CONTEXT_CONTROL_D8_OFFSET,
40    ARM_CONTEXT_CONTROL_D8_OFFSET
41  );
42#endif
43
44RTEMS_STATIC_ASSERT(
45  sizeof( CPU_Exception_frame ) == ARM_EXCEPTION_FRAME_SIZE,
46  ARM_EXCEPTION_FRAME_SIZE
47);
48
49RTEMS_STATIC_ASSERT(
50  offsetof( CPU_Exception_frame, register_sp )
51    == ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET,
52  ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET
53);
54
55RTEMS_STATIC_ASSERT(
56  sizeof( ARM_VFP_context ) == ARM_VFP_CONTEXT_SIZE,
57  ARM_VFP_CONTEXT_SIZE
58);
59
60#ifdef ARM_MULTILIB_ARCH_V4
61
62/*
63 * This variable can be used to change the running mode of the execution
64 * contexts.
65 */
66uint32_t arm_cpu_mode = 0x13;
67
68void _CPU_Context_Initialize(
69  Context_Control *the_context,
70  void *stack_area_begin,
71  size_t stack_area_size,
72  uint32_t new_level,
73  void (*entry_point)( void ),
74  bool is_fp
75)
76{
77  the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size;
78  the_context->register_lr = (uint32_t) entry_point;
79  the_context->register_cpsr = new_level | arm_cpu_mode;
80}
81
82/* Preprocessor magic for stringification of x */
83#define _CPU_ISR_LEVEL_DO_STRINGOF( x) #x
84#define _CPU_ISR_LEVEL_STRINGOF( x) _CPU_ISR_LEVEL_DO_STRINGOF( x)
85
86void _CPU_ISR_Set_level( uint32_t level )
87{
88  uint32_t arm_switch_reg;
89
90  __asm__ volatile (
91    ARM_SWITCH_TO_ARM
92    "mrs %[arm_switch_reg], cpsr\n"
93    "bic %[arm_switch_reg], #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n"
94    "orr %[arm_switch_reg], %[level]\n"
95    "msr cpsr, %0\n"
96    ARM_SWITCH_BACK
97    : [arm_switch_reg] "=&r" (arm_switch_reg)
98    : [level] "r" (level)
99  );
100}
101
102uint32_t _CPU_ISR_Get_level( void )
103{
104  ARM_SWITCH_REGISTERS;
105  uint32_t level;
106
107  __asm__ volatile (
108    ARM_SWITCH_TO_ARM
109    "mrs %[level], cpsr\n"
110    "and %[level], #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n"
111    ARM_SWITCH_BACK
112    : [level] "=&r" (level) ARM_SWITCH_ADDITIONAL_OUTPUT
113  );
114
115  return level;
116}
117
118void _CPU_ISR_install_vector(
119  uint32_t vector,
120  proc_ptr new_handler,
121  proc_ptr *old_handler
122)
123{
124  /* Redirection table starts at the end of the vector table */
125  volatile uint32_t *table = (volatile uint32_t *) (MAX_EXCEPTIONS * 4);
126
127  uint32_t current_handler = table [vector];
128
129  /* The current handler is now the old one */
130  if (old_handler != NULL) {
131    *old_handler = (proc_ptr) current_handler;
132  }
133
134  /* Write only if necessary to avoid writes to a maybe read-only memory */
135  if (current_handler != (uint32_t) new_handler) {
136    table [vector] = (uint32_t) new_handler;
137  }
138}
139
140void _CPU_Initialize( void )
141{
142  /* Do nothing */
143}
144
145#endif /* ARM_MULTILIB_ARCH_V4 */
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