source: rtems/cpukit/score/cpu/arm/cpu.c @ c5ed148

4.115
Last change on this file since c5ed148 was c5ed148, checked in by Sebastian Huber <sebastian.huber@…>, on 09/24/11 at 12:56:51

2011-09-24 Sebastian Huber <sebastian.huber@…>

  • rtems/score/armv7m.h, armv7m-context-initialize.c, armv7m-context-restore.c, armv7m-context-switch.c, armv7m-exception-handler-get.c, armv7m-exception-handler-set.c, armv7m-exception-priority-get.c, armv7m-exception-priority-set.c, armv7m-initialize.c, armv7m-isr-dispatch.c, armv7m-isr-enter-leave.c, armv7m-isr-level-get.c, armv7m-isr-level-set.c, armv7m-isr-vector-install.c, armv7m-multitasking-start-stop.c: New files.
  • Makefile.am, preinstall.am: Reflect changes above.
  • rtems/score/arm.h: Define ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M.
  • rtems/score/cpu.h, cpu_asm.S, cpu.c, arm_exc_abort.S, arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S: Define CPU_HAS_HARDWARE_INTERRUPT_STACK to FALSE. Use ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M.
  • Property mode set to 100644
File size: 2.9 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup ScoreCPU
5 *
6 * @brief ARM architecture support implementation.
7 */
8
9/*
10 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
11 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
12 *
13 *  Copyright (c) 2002 Advent Networks, Inc
14 *      Jay Monkman <jmonkman@adventnetworks.com>
15 *
16 *  Copyright (c) 2007 Ray xu <rayx.cn@gmail.com>
17 *
18 *  Copyright (c) 2009-2011 embedded brains GmbH
19 *
20 *  The license and distribution terms for this file may be
21 *  found in the file LICENSE in this distribution or at
22 *  http://www.rtems.com/license/LICENSE.
23 *
24 *  $Id$
25 */
26
27#ifdef HAVE_CONFIG_H
28#include "config.h"
29#endif
30
31#include <rtems/system.h>
32#include <rtems.h>
33#include <rtems/bspIo.h>
34#include <rtems/score/isr.h>
35#include <rtems/score/wkspace.h>
36#include <rtems/score/thread.h>
37#include <rtems/score/cpu.h>
38
39#ifdef ARM_MULTILIB_ARCH_V4
40
41/*
42 * This variable can be used to change the running mode of the execution
43 * contexts.
44 */
45uint32_t arm_cpu_mode = 0x13;
46
47void _CPU_Context_Initialize(
48  Context_Control *the_context,
49  void *stack_area_begin,
50  size_t stack_area_size,
51  uint32_t new_level,
52  void (*entry_point)( void ),
53  bool is_fp
54)
55{
56  the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size;
57  the_context->register_lr = (uint32_t) entry_point;
58  the_context->register_cpsr = new_level | arm_cpu_mode;
59}
60
61/* Preprocessor magic for stringification of x */
62#define _CPU_ISR_LEVEL_DO_STRINGOF( x) #x
63#define _CPU_ISR_LEVEL_STRINGOF( x) _CPU_ISR_LEVEL_DO_STRINGOF( x)
64
65void _CPU_ISR_Set_level( uint32_t level )
66{
67  uint32_t arm_switch_reg;
68
69  __asm__ volatile (
70    ARM_SWITCH_TO_ARM
71    "mrs %[arm_switch_reg], cpsr\n"
72    "bic %[arm_switch_reg], #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n"
73    "orr %[arm_switch_reg], %[level]\n"
74    "msr cpsr, %0\n"
75    ARM_SWITCH_BACK
76    : [arm_switch_reg] "=&r" (arm_switch_reg)
77    : [level] "r" (level)
78  );
79}
80
81uint32_t _CPU_ISR_Get_level( void )
82{
83  ARM_SWITCH_REGISTERS;
84  uint32_t level;
85
86  __asm__ volatile (
87    ARM_SWITCH_TO_ARM
88    "mrs %[level], cpsr\n"
89    "and %[level], #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n"
90    ARM_SWITCH_BACK
91    : [level] "=&r" (level) ARM_SWITCH_ADDITIONAL_OUTPUT
92  );
93
94  return level;
95}
96
97void _CPU_ISR_install_vector(
98  uint32_t vector,
99  proc_ptr new_handler,
100  proc_ptr *old_handler
101)
102{
103  /* Redirection table starts at the end of the vector table */
104  volatile uint32_t *table = (volatile uint32_t *) (MAX_EXCEPTIONS * 4);
105
106  uint32_t current_handler = table [vector];
107
108  /* The current handler is now the old one */
109  if (old_handler != NULL) {
110    *old_handler = (proc_ptr) current_handler;
111  }
112
113  /* Write only if necessary to avoid writes to a maybe read-only memory */
114  if (current_handler != (uint32_t) new_handler) {
115    table [vector] = (uint32_t) new_handler;
116  }
117}
118
119void _CPU_Initialize( void )
120{
121  /* Do nothing */
122}
123
124#endif /* ARM_MULTILIB_ARCH_V4 */
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