1 | /* |
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2 | * ARM CPU Dependent Source |
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3 | * |
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4 | * |
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5 | * COPYRIGHT (c) 2000 Canon Research Centre France SA. |
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6 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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7 | * |
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8 | * Copyright (c) 2002 Advent Networks, Inc |
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9 | * Jay Monkman <jmonkman@adventnetworks.com> |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.OARcorp.com/rtems/license.html. |
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14 | * |
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15 | */ |
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16 | |
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17 | #include <rtems/system.h> |
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18 | #include <rtems.h> |
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19 | #include <rtems/bspIo.h> |
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20 | #include <rtems/score/isr.h> |
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21 | #include <rtems/score/wkspace.h> |
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22 | #include <rtems/score/thread.h> |
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23 | #include <rtems/score/cpu.h> |
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24 | |
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25 | /* _CPU_Initialize |
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26 | * |
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27 | * This routine performs processor dependent initialization. |
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28 | * |
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29 | * INPUT PARAMETERS: |
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30 | * cpu_table - CPU table to initialize |
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31 | * thread_dispatch - address of ISR disptaching routine (unused) |
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32 | * |
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33 | */ |
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34 | |
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35 | unsigned32 g_data_abort_cnt = 0; |
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36 | unsigned32 g_data_abort_insn_list[1024]; |
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37 | |
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38 | void _CPU_Initialize( |
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39 | rtems_cpu_table *cpu_table, |
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40 | void (*thread_dispatch) /* ignored on this CPU */ |
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41 | ) |
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42 | { |
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43 | _CPU_Table = *cpu_table; |
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44 | } |
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45 | |
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46 | /* |
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47 | * |
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48 | * _CPU_ISR_Get_level - returns the current interrupt level |
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49 | */ |
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50 | |
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51 | unsigned32 _CPU_ISR_Get_level( void ) |
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52 | { |
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53 | unsigned32 reg; |
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54 | |
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55 | asm volatile ("mrs %0, cpsr \n" \ |
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56 | "and %0, %0, #0xc0 \n" \ |
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57 | : "=r" (reg) \ |
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58 | : "0" (reg) ); |
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59 | |
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60 | return reg; |
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61 | } |
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62 | |
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63 | /* |
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64 | * _CPU_ISR_install_vector |
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65 | * |
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66 | * This kernel routine installs the RTEMS handler for the |
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67 | * specified vector. |
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68 | * |
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69 | * Input parameters: |
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70 | * vector - interrupt vector number |
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71 | * new_handler - replacement ISR for this vector number |
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72 | * old_handler - pointer to store former ISR for this vector number |
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73 | * |
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74 | * FIXME: This vector scheme should be changed to allow FIQ to be |
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75 | * handled better. I'd like to be able to put VectorTable |
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76 | * elsewhere - JTM |
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77 | * |
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78 | * |
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79 | * Output parameters: NONE |
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80 | * |
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81 | */ |
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82 | void _CPU_ISR_install_vector( |
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83 | unsigned32 vector, |
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84 | proc_ptr new_handler, |
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85 | proc_ptr *old_handler |
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86 | ) |
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87 | { |
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88 | /* pointer on the redirection table in RAM */ |
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89 | long *VectorTable = (long *)(MAX_EXCEPTIONS * 4); |
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90 | |
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91 | if (old_handler != NULL) { |
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92 | old_handler = *(proc_ptr *)(VectorTable + vector); |
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93 | } |
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94 | |
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95 | *(VectorTable + vector) = (long)new_handler ; |
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96 | |
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97 | } |
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98 | |
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99 | void _CPU_Context_Initialize( |
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100 | Context_Control *the_context, |
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101 | unsigned32 *stack_base, |
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102 | unsigned32 size, |
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103 | unsigned32 new_level, |
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104 | void *entry_point, |
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105 | boolean is_fp |
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106 | ) |
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107 | { |
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108 | the_context->register_sp = (unsigned32)stack_base + size ; |
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109 | the_context->register_lr = (unsigned32)entry_point; |
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110 | the_context->register_cpsr = new_level | 0x13; |
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111 | } |
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112 | |
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113 | |
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114 | /* |
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115 | * _CPU_Install_interrupt_stack - this function is empty since the |
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116 | * BSP must set up the interrupt stacks. |
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117 | */ |
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118 | |
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119 | void _CPU_Install_interrupt_stack( void ) |
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120 | { |
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121 | } |
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122 | |
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123 | void _defaultExcHandler (CPU_Exception_frame *ctx) |
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124 | { |
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125 | printk("\n\r"); |
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126 | printk("----------------------------------------------------------\n\r"); |
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127 | #if 0 |
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128 | printk("Exception 0x%x caught at PC 0x%x by thread %d\n", |
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129 | ctx->register_pc, ctx->register_lr - 4, |
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130 | _Thread_Executing->Object.id); |
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131 | #endif |
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132 | printk("----------------------------------------------------------\n\r"); |
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133 | printk("Processor execution context at time of the fault was :\n\r"); |
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134 | printk("----------------------------------------------------------\n\r"); |
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135 | #if 0 |
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136 | printk(" r0 = %8x r1 = %8x r2 = %8x r3 = %8x\n\r", |
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137 | ctx->register_r0, ctx->register_r1, |
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138 | ctx->register_r2, ctx->register_r3); |
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139 | printk(" r4 = %8x r5 = %8x r6 = %8x r7 = %8x\n\r", |
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140 | ctx->register_r4, ctx->register_r5, |
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141 | ctx->register_r6, ctx->register_r7); |
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142 | printk(" r8 = %8x r9 = %8x r10 = %8x\n\r", |
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143 | ctx->register_r8, ctx->register_r9, ctx->register_r10); |
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144 | printk(" fp = %8x ip = %8x sp = %8x pc = %8x\n\r", |
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145 | ctx->register_fp, ctx->register_ip, |
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146 | ctx->register_sp, ctx->register_lr - 4); |
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147 | printk("----------------------------------------------------------\n\r"); |
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148 | #endif |
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149 | if (_ISR_Nest_level > 0) { |
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150 | /* |
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151 | * In this case we shall not delete the task interrupted as |
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152 | * it has nothing to do with the fault. We cannot return either |
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153 | * because the eip points to the faulty instruction so... |
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154 | */ |
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155 | printk("Exception while executing ISR!!!. System locked\n\r"); |
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156 | while(1); |
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157 | } |
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158 | else { |
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159 | printk("*********** FAULTY THREAD WILL BE DELETED **************\n\r"); |
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160 | rtems_task_delete(_Thread_Executing->Object.id); |
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161 | } |
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162 | } |
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163 | |
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164 | cpuExcHandlerType _currentExcHandler = _defaultExcHandler; |
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165 | |
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166 | extern void _Exception_Handler_Undef_Swi(); |
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167 | extern void _Exception_Handler_Abort(); |
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168 | extern void _exc_data_abort(); |
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169 | /* FIXME: put comments here */ |
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170 | void rtems_exception_init_mngt() |
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171 | { |
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172 | ISR_Level level; |
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173 | |
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174 | _CPU_ISR_Disable(level); |
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175 | _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF, |
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176 | _Exception_Handler_Undef_Swi, |
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177 | NULL); |
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178 | |
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179 | _CPU_ISR_install_vector(ARM_EXCEPTION_SWI, |
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180 | _Exception_Handler_Undef_Swi, |
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181 | NULL); |
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182 | |
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183 | _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, |
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184 | _Exception_Handler_Abort, |
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185 | NULL); |
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186 | |
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187 | _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, |
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188 | _exc_data_abort, |
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189 | NULL); |
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190 | |
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191 | _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ, |
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192 | _Exception_Handler_Abort, |
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193 | NULL); |
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194 | |
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195 | _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, |
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196 | _Exception_Handler_Abort, |
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197 | NULL); |
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198 | |
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199 | _CPU_ISR_Enable(level); |
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200 | } |
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201 | |
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202 | #define INSN_MASK 0xc5 |
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203 | |
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204 | #define INSN_STM1 0x80 |
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205 | #define INSN_STM2 0x84 |
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206 | #define INSN_STR 0x40 |
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207 | #define INSN_STRB 0x44 |
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208 | |
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209 | #define INSN_LDM1 0x81 |
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210 | #define INSN_LDM23 0x85 |
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211 | #define INSN_LDR 0x41 |
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212 | #define INSN_LDRB 0x45 |
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213 | |
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214 | #define GET_RD(x) ((x & 0x0000f000) >> 12) |
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215 | #define GET_RN(x) ((x & 0x000f0000) >> 16) |
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216 | |
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217 | #define GET_U(x) ((x & 0x00800000) >> 23) |
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218 | #define GET_I(x) ((x & 0x02000000) >> 25) |
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219 | |
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220 | #define GET_REG(r, ctx) (((unsigned32 *)ctx)[r]) |
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221 | #define SET_REG(r, ctx, v) (((unsigned32 *)ctx)[r] = v) |
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222 | #define GET_OFFSET(insn) (insn & 0xfff) |
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223 | |
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224 | |
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225 | /* This function is supposed to figure out what caused the |
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226 | * data abort, do that, then return. |
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227 | * |
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228 | * All unhandled instructions cause the system to hang. |
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229 | */ |
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230 | |
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231 | void do_data_abort(unsigned32 insn, unsigned32 spsr, |
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232 | CPU_Exception_frame *ctx) |
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233 | { |
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234 | unsigned8 decode; |
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235 | unsigned8 insn_type; |
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236 | |
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237 | unsigned32 rn; |
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238 | unsigned32 rd; |
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239 | |
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240 | unsigned8 *src_addr; |
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241 | unsigned8 *dest_addr; |
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242 | unsigned32 tmp; |
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243 | |
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244 | g_data_abort_insn_list[g_data_abort_cnt & 0x3ff] = ctx->register_lr - 8; |
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245 | g_data_abort_cnt++; |
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246 | |
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247 | decode = ((insn >> 20) & 0xff); |
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248 | |
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249 | insn_type = decode & INSN_MASK; |
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250 | switch(insn_type) { |
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251 | case INSN_STM1: |
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252 | printk("\n\nINSN_STM1\n"); |
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253 | break; |
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254 | case INSN_STM2: |
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255 | printk("\n\nINSN_STM2\n"); |
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256 | break; |
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257 | case INSN_STR: |
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258 | printk("\n\nINSN_STR\n"); |
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259 | break; |
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260 | case INSN_STRB: |
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261 | printk("\n\nINSN_STRB\n"); |
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262 | break; |
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263 | case INSN_LDM1: |
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264 | printk("\n\nINSN_LDM1\n"); |
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265 | break; |
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266 | case INSN_LDM23: |
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267 | printk("\n\nINSN_LDM23\n"); |
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268 | break; |
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269 | case INSN_LDR: |
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270 | printk("\n\nINSN_LDR\n"); |
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271 | |
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272 | rn = GET_RN(insn); |
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273 | rd = GET_RD(insn); |
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274 | |
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275 | /* immediate offset/index */ |
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276 | if (GET_I(insn) == 0) { |
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277 | switch(decode & 0x12) { /* P and W bits */ |
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278 | case 0x00: /* P=0, W=0 -> base is updated, post-indexed */ |
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279 | printk("\tPost-indexed\n"); |
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280 | break; |
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281 | case 0x02: /* P=0, W=1 -> user mode access */ |
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282 | printk("\tUser mode\n"); |
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283 | break; |
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284 | case 0x10: /* P=1, W=0 -> base not updated */ |
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285 | src_addr = GET_REG(rn, ctx); |
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286 | if (GET_U(insn) == 0) { |
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287 | src_addr -= GET_OFFSET(insn); |
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288 | } else { |
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289 | src_addr += GET_OFFSET(insn); |
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290 | } |
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291 | tmp = (src_addr[0] | |
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292 | (src_addr[1] << 8) | |
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293 | (src_addr[2] << 16) | |
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294 | (src_addr[3] << 24)); |
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295 | SET_REG(rd, ctx, tmp); |
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296 | return; |
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297 | break; |
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298 | case 0x12: /* P=1, W=1 -> base is updated, pre-indexed */ |
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299 | printk("\tPre-indexed\n"); |
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300 | break; |
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301 | } |
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302 | } |
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303 | break; |
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304 | case INSN_LDRB: |
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305 | printk("\n\nINSN_LDRB\n"); |
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306 | break; |
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307 | default: |
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308 | printk("\n\nUnrecognized instruction\n"); |
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309 | break; |
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310 | } |
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311 | |
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312 | printk("data_abort at address 0x%x, instruction: 0x%x, spsr = 0x%x\n", |
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313 | ctx->register_lr - 8, insn, spsr); |
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314 | |
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315 | /* disable interrupts, wait forever */ |
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316 | _CPU_ISR_Disable(tmp); |
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317 | while(1) { |
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318 | continue; |
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319 | } |
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320 | return; |
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321 | } |
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322 | |
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323 | |
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324 | |
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