1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup ScoreCPU |
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5 | * |
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6 | * @brief ARM architecture support implementation. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * COPYRIGHT (c) 2000 Canon Research Centre France SA. |
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11 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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12 | * |
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13 | * Copyright (c) 2002 Advent Networks, Inc |
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14 | * Jay Monkman <jmonkman@adventnetworks.com> |
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15 | * |
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16 | * Copyright (c) 2007 Ray xu <rayx.cn@gmail.com> |
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17 | * |
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18 | * Copyright (c) 2009 embedded brains GmbH |
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19 | * |
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20 | * The license and distribution terms for this file may be |
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21 | * found in the file LICENSE in this distribution or at |
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22 | * http://www.rtems.com/license/LICENSE. |
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23 | * |
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24 | * $Id$ |
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25 | */ |
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26 | |
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27 | #ifdef HAVE_CONFIG_H |
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28 | #include "config.h" |
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29 | #endif |
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30 | |
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31 | #include <rtems/system.h> |
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32 | #include <rtems.h> |
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33 | #include <rtems/bspIo.h> |
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34 | #include <rtems/score/isr.h> |
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35 | #include <rtems/score/wkspace.h> |
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36 | #include <rtems/score/thread.h> |
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37 | #include <rtems/score/cpu.h> |
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38 | |
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39 | /* |
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40 | * This variable can be used to change the running mode of the execution |
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41 | * contexts. |
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42 | */ |
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43 | uint32_t arm_cpu_mode = 0x13; |
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44 | |
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45 | void _CPU_Context_Initialize( |
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46 | Context_Control *the_context, |
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47 | uint32_t *stack_base, |
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48 | uint32_t size, |
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49 | uint32_t new_level, |
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50 | void *entry_point, |
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51 | bool is_fp |
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52 | ) |
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53 | { |
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54 | the_context->register_sp = (uint32_t) stack_base + size ; |
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55 | the_context->register_lr = (uint32_t) entry_point; |
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56 | the_context->register_cpsr = new_level | arm_cpu_mode; |
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57 | } |
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58 | |
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59 | /* Preprocessor magic for stringification of x */ |
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60 | #define _CPU_ISR_LEVEL_DO_STRINGOF( x) #x |
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61 | #define _CPU_ISR_LEVEL_STRINGOF( x) _CPU_ISR_LEVEL_DO_STRINGOF( x) |
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62 | |
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63 | void _CPU_ISR_Set_level( uint32_t level ) |
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64 | { |
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65 | uint32_t arm_switch_reg; |
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66 | |
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67 | asm volatile ( |
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68 | ARM_SWITCH_TO_ARM |
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69 | "mrs %[arm_switch_reg], cpsr\n" |
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70 | "bic %[arm_switch_reg], #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n" |
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71 | "orr %[arm_switch_reg], %[level]\n" |
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72 | "msr cpsr, %0\n" |
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73 | ARM_SWITCH_BACK |
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74 | : [arm_switch_reg] "=&r" (arm_switch_reg) |
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75 | : [level] "r" (level) |
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76 | ); |
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77 | } |
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78 | |
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79 | uint32_t _CPU_ISR_Get_level( void ) |
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80 | { |
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81 | ARM_SWITCH_REGISTERS; |
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82 | uint32_t level; |
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83 | |
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84 | asm volatile ( |
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85 | ARM_SWITCH_TO_ARM |
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86 | "mrs %[level], cpsr\n" |
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87 | "and %[level], #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n" |
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88 | ARM_SWITCH_BACK |
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89 | : [level] "=&r" (level) ARM_SWITCH_ADDITIONAL_OUTPUT |
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90 | ); |
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91 | |
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92 | return level; |
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93 | } |
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94 | |
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95 | void _CPU_ISR_install_vector( |
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96 | uint32_t vector, |
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97 | proc_ptr new_handler, |
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98 | proc_ptr *old_handler |
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99 | ) |
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100 | { |
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101 | /* Redirection table starts at the end of the vector table */ |
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102 | volatile uint32_t *table = (volatile uint32_t *) (MAX_EXCEPTIONS * 4); |
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103 | |
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104 | uint32_t current_handler = table [vector]; |
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105 | |
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106 | /* The current handler is now the old one */ |
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107 | if (old_handler != NULL) { |
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108 | *old_handler = (proc_ptr) current_handler; |
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109 | } |
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110 | |
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111 | /* Write only if necessary to avoid writes to a maybe read-only memory */ |
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112 | if (current_handler != (uint32_t) new_handler) { |
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113 | table [vector] = (uint32_t) new_handler; |
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114 | } |
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115 | } |
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116 | |
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117 | void _CPU_Install_interrupt_stack( void ) |
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118 | { |
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119 | /* This function is empty since the BSP must set up the interrupt stacks */ |
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120 | } |
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121 | |
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122 | void _CPU_Initialize( void ) |
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123 | { |
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124 | /* Do nothing */ |
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125 | } |
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