source: rtems/cpukit/score/cpu/arm/cpu.c @ 60f016f

4.104.114.84.95
Last change on this file since 60f016f was 60f016f, checked in by Joel Sherrill <joel.sherrill@…>, on May 22, 2007 at 8:57:34 PM

2007-05-22 Joel Sherrill <joel.sherrill@…>

  • score/cpu/arm/cpu.c, score/cpu/avr/cpu.c, score/cpu/bfin/cpu.c, score/cpu/c4x/cpu.c, score/cpu/h8300/cpu.c, score/cpu/i386/cpu.c, score/cpu/m68k/cpu.c, score/cpu/mips/cpu.c, score/cpu/nios2/cpu.c, score/cpu/no_cpu/cpu.c, score/cpu/sh/cpu.c, score/cpu/sparc/cpu.c, cpukit/sapi/src/exinit.c: Move copying of CPU Table to shared executive initialization.
  • Property mode set to 100644
File size: 6.3 KB
Line 
1/*
2 *  ARM CPU Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
6 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
7 *
8 *  Copyright (c) 2002 Advent Networks, Inc
9 *      Jay Monkman <jmonkman@adventnetworks.com>
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 */
16
17#include <rtems/system.h>
18#include <rtems.h>
19#include <rtems/bspIo.h>
20#include <rtems/score/isr.h>
21#include <rtems/score/wkspace.h>
22#include <rtems/score/thread.h>
23#include <rtems/score/cpu.h>
24
25/*  _CPU_Initialize
26 *
27 *  This routine performs processor dependent initialization.
28 *
29 *  INPUT PARAMETERS:
30 *    cpu_table       - CPU table to initialize
31 *    thread_dispatch - address of ISR disptaching routine (unused)
32 *   
33 */
34
35void _CPU_Initialize(
36  rtems_cpu_table  *cpu_table,
37  void      (*thread_dispatch)      /* ignored on this CPU */
38)
39{
40}
41
42/*
43 *
44 *  _CPU_ISR_Get_level - returns the current interrupt level
45 */
46 
47uint32_t   _CPU_ISR_Get_level( void )
48{
49    uint32_t   reg = 0; /* to avoid warning */
50   
51    asm volatile ("mrs  %0, cpsr \n"           \
52                  "and  %0,  %0, #0xc0 \n"     \
53                  : "=r" (reg)                 \
54                  : "0" (reg) );
55   
56    return reg;
57}
58
59/*
60 *  _CPU_ISR_install_vector
61 *
62 *  This kernel routine installs the RTEMS handler for the
63 *  specified vector.
64 *
65 *  Input parameters:
66 *    vector      - interrupt vector number
67 *    new_handler - replacement ISR for this vector number
68 *    old_handler - pointer to store former ISR for this vector number
69 *
70 *  FIXME: This vector scheme should be changed to allow FIQ to be
71 *         handled better. I'd like to be able to put VectorTable
72 *         elsewhere - JTM
73 *
74 *
75 *  Output parameters:  NONE
76 *
77 */
78void _CPU_ISR_install_vector(
79  uint32_t    vector,
80  proc_ptr    new_handler,
81  proc_ptr   *old_handler
82)
83{
84    /* pointer on the redirection table in RAM */
85    long *VectorTable = (long *)(MAX_EXCEPTIONS * 4); 
86   
87    if (old_handler != NULL) {
88        old_handler = *(proc_ptr *)(VectorTable + vector);
89    }
90
91    *(VectorTable + vector) = (long)new_handler ;
92 
93}
94
95void _CPU_Context_Initialize(
96  Context_Control  *the_context,
97  uint32_t         *stack_base,
98  uint32_t          size,
99  uint32_t          new_level,
100  void             *entry_point,
101  boolean           is_fp
102)
103{
104    the_context->register_sp = (uint32_t  )stack_base + size ;
105    the_context->register_lr = (uint32_t  )entry_point;
106    the_context->register_cpsr = new_level | 0x13;
107}
108
109
110/*
111 *  _CPU_Install_interrupt_stack - this function is empty since the
112 *  BSP must set up the interrupt stacks.
113 */
114
115void _CPU_Install_interrupt_stack( void )
116{
117}
118
119void _defaultExcHandler (CPU_Exception_frame *ctx)
120{
121    printk("\n\r");
122    printk("----------------------------------------------------------\n\r");
123#if 1
124    printk("Exception 0x%x caught at PC 0x%x by thread %d\n",
125           ctx->register_ip, ctx->register_lr - 4,
126           _Thread_Executing->Object.id);
127#endif
128    printk("----------------------------------------------------------\n\r");
129    printk("Processor execution context at time of the fault was  :\n\r");
130    printk("----------------------------------------------------------\n\r");
131#if 0
132    printk(" r0  = %8x  r1  = %8x  r2  = %8x  r3  = %8x\n\r",
133           ctx->register_r0, ctx->register_r1,
134           ctx->register_r2, ctx->register_r3);
135    printk(" r4  = %8x  r5  = %8x  r6  = %8x  r7  = %8x\n\r",
136           ctx->register_r4, ctx->register_r5,
137           ctx->register_r6, ctx->register_r7);
138    printk(" r8  = %8x  r9  = %8x  r10 = %8x\n\r",
139           ctx->register_r8, ctx->register_r9, ctx->register_r10);
140    printk(" fp  = %8x  ip  = %8x  sp  = %8x  pc  = %8x\n\r",
141           ctx->register_fp, ctx->register_ip,
142           ctx->register_sp, ctx->register_lr - 4);
143    printk("----------------------------------------------------------\n\r");
144#endif   
145    if (_ISR_Nest_level > 0) {
146        /*
147         * In this case we shall not delete the task interrupted as
148         * it has nothing to do with the fault. We cannot return either
149         * because the eip points to the faulty instruction so...
150         */
151        printk("Exception while executing ISR!!!. System locked\n\r");
152        while(1);
153    }
154    else {
155        printk("*********** FAULTY THREAD WILL BE DELETED **************\n\r");
156        rtems_task_delete(_Thread_Executing->Object.id);
157    }
158}
159
160cpuExcHandlerType _currentExcHandler = _defaultExcHandler;
161
162extern void _Exception_Handler_Undef_Swi(); 
163extern void _Exception_Handler_Abort(); 
164extern void _exc_data_abort(); 
165/* FIXME: put comments here */
166void rtems_exception_init_mngt()
167{
168        ISR_Level level;
169     
170      _CPU_ISR_Disable(level);
171      _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,
172                              _Exception_Handler_Undef_Swi,
173                              NULL);
174 
175      _CPU_ISR_install_vector(ARM_EXCEPTION_SWI,
176                              _Exception_Handler_Undef_Swi,
177                              NULL);
178     
179      _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT,
180                              _Exception_Handler_Abort,
181                              NULL);
182     
183      _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT,
184                              _exc_data_abort,
185                              NULL);
186     
187      _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,       
188                              _Exception_Handler_Abort,
189                              NULL);
190     
191      _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, 
192                              _Exception_Handler_Abort,
193                              NULL);
194     
195      _CPU_ISR_Enable(level);
196}
197 
198#define INSN_MASK         0xc5
199
200#define INSN_STM1         0x80
201#define INSN_STM2         0x84
202#define INSN_STR          0x40
203#define INSN_STRB         0x44
204
205#define INSN_LDM1         0x81
206#define INSN_LDM23        0x85
207#define INSN_LDR          0x41
208#define INSN_LDRB         0x45
209
210#define GET_RD(x)         ((x & 0x0000f000) >> 12)
211#define GET_RN(x)         ((x & 0x000f0000) >> 16)
212
213#define GET_U(x)              ((x & 0x00800000) >> 23)
214#define GET_I(x)              ((x & 0x02000000) >> 25)
215
216#define GET_REG(r, ctx)      (((uint32_t   *)ctx)[r])
217#define SET_REG(r, ctx, v)   (((uint32_t   *)ctx)[r] = v)
218#define GET_OFFSET(insn)     (insn & 0xfff)
219
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