1 | /* |
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2 | * ARM CPU Dependent Source |
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3 | * |
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4 | * |
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5 | * COPYRIGHT (c) 2000 Canon Research Centre France SA. |
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6 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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7 | * |
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8 | * Copyright (c) 2002 Advent Networks, Inc |
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9 | * Jay Monkman <jmonkman@adventnetworks.com> |
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10 | * |
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11 | * Copyright (c) 2007 Ray xu <rayx.cn@gmail.com> |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.com/license/LICENSE. |
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16 | * |
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17 | * $Id$ |
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18 | */ |
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19 | |
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20 | #include <rtems/system.h> |
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21 | #include <rtems.h> |
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22 | #include <rtems/bspIo.h> |
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23 | #include <rtems/score/isr.h> |
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24 | #include <rtems/score/wkspace.h> |
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25 | #include <rtems/score/thread.h> |
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26 | #include <rtems/score/cpu.h> |
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27 | |
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28 | /* |
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29 | * This variable can be used to change the running mode of the execution |
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30 | * contexts. |
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31 | */ |
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32 | |
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33 | unsigned int arm_cpu_mode = 0x13; |
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34 | |
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35 | /* _CPU_Initialize |
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36 | * |
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37 | * This routine performs processor dependent initialization. |
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38 | * |
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39 | * INPUT PARAMETERS: |
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40 | * thread_dispatch - address of ISR disptaching routine (unused) |
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41 | */ |
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42 | |
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43 | void _CPU_Initialize( |
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44 | void (*thread_dispatch) /* ignored on this CPU */ |
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45 | ) |
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46 | { |
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47 | } |
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48 | |
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49 | /* |
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50 | * |
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51 | * _CPU_ISR_Get_level - returns the current interrupt level |
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52 | */ |
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53 | #define str(x) #x |
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54 | #define xstr(x) str(x) |
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55 | #define L(x) #x "_" xstr(__LINE__) |
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56 | |
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57 | #define TO_ARM_MODE(x) \ |
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58 | asm volatile ( \ |
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59 | ".code 16 \n" \ |
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60 | L(x) "_thumb: \n" \ |
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61 | ".align 2 \n" \ |
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62 | "push {lr} \n" \ |
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63 | "adr %0, "L(x) "_arm \n" \ |
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64 | "bl " L(x)" \n" \ |
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65 | "pop {pc} \n" \ |
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66 | ".balign 4 \n" \ |
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67 | L(x) ": \n" \ |
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68 | "bx %0 \n" \ |
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69 | "nop \n" \ |
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70 | ".pool \n" \ |
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71 | ".code 32 \n" \ |
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72 | L(x) "_arm: \n" \ |
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73 | :"=&r" (reg)) |
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74 | |
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75 | |
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76 | /* |
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77 | * Switch to Thumb mode Veneer,ugly but safe |
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78 | */ |
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79 | |
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80 | #define TO_THUMB_MODE(x) \ |
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81 | asm volatile ( \ |
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82 | ".code 32 \n"\ |
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83 | "adr %0, "L(x) "_thumb +1 \n"\ |
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84 | "bx %0 \n"\ |
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85 | ".pool \n"\ |
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86 | ".thumb_func \n"\ |
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87 | L(x) "_thumb: \n"\ |
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88 | : "=&r" (reg)) |
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89 | |
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90 | #if (!defined(__THUMB_INTERWORK__) && !defined(__thumb__)) |
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91 | uint32_t _CPU_ISR_Get_level( void ) |
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92 | { |
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93 | uint32_t reg = 0; /* to avoid warning */ |
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94 | asm volatile ("mrs %0, cpsr \n" \ |
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95 | "and %0, %0, #0xc0 \n" \ |
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96 | : "=r" (reg) \ |
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97 | : "0" (reg) ); |
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98 | return reg; |
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99 | } |
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100 | #endif |
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101 | |
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102 | |
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103 | |
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104 | /* |
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105 | * _CPU_ISR_install_vector |
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106 | * |
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107 | * This kernel routine installs the RTEMS handler for the |
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108 | * specified vector. |
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109 | * |
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110 | * Input parameters: |
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111 | * vector - interrupt vector number |
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112 | * new_handler - replacement ISR for this vector number |
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113 | * old_handler - pointer to store former ISR for this vector number |
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114 | * |
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115 | * FIXME: This vector scheme should be changed to allow FIQ to be |
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116 | * handled better. I'd like to be able to put VectorTable |
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117 | * elsewhere - JTM |
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118 | * |
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119 | * |
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120 | * Output parameters: NONE |
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121 | * |
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122 | */ |
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123 | void _CPU_ISR_install_vector( |
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124 | uint32_t vector, |
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125 | proc_ptr new_handler, |
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126 | proc_ptr *old_handler |
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127 | ) |
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128 | { |
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129 | /* pointer on the redirection table in RAM */ |
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130 | long *VectorTable = (long *)(MAX_EXCEPTIONS * 4); |
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131 | |
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132 | if (old_handler != NULL) { |
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133 | old_handler = *(proc_ptr *)(VectorTable + vector); |
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134 | } |
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135 | |
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136 | *(VectorTable + vector) = (long)new_handler ; |
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137 | |
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138 | } |
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139 | |
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140 | void _CPU_Context_Initialize( |
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141 | Context_Control *the_context, |
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142 | uint32_t *stack_base, |
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143 | uint32_t size, |
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144 | uint32_t new_level, |
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145 | void *entry_point, |
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146 | bool is_fp |
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147 | ) |
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148 | { |
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149 | the_context->register_sp = (uint32_t )stack_base + size ; |
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150 | the_context->register_lr = (uint32_t )entry_point; |
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151 | the_context->register_cpsr = new_level | arm_cpu_mode; |
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152 | } |
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153 | |
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154 | |
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155 | /* |
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156 | * _CPU_Install_interrupt_stack - this function is empty since the |
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157 | * BSP must set up the interrupt stacks. |
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158 | */ |
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159 | |
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160 | void _CPU_Install_interrupt_stack( void ) |
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161 | { |
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162 | } |
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163 | |
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164 | void _defaultExcHandler (CPU_Exception_frame *ctx) |
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165 | { |
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166 | printk("\n\r"); |
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167 | printk("----------------------------------------------------------\n\r"); |
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168 | #if 1 |
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169 | printk("Exception 0x%x caught at PC 0x%x by thread %d\n", |
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170 | ctx->register_ip, ctx->register_lr - 4, |
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171 | _Thread_Executing->Object.id); |
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172 | #endif |
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173 | printk("----------------------------------------------------------\n\r"); |
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174 | printk("Processor execution context at time of the fault was :\n\r"); |
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175 | printk("----------------------------------------------------------\n\r"); |
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176 | #if 0 |
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177 | printk(" r0 = %8x r1 = %8x r2 = %8x r3 = %8x\n\r", |
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178 | ctx->register_r0, ctx->register_r1, |
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179 | ctx->register_r2, ctx->register_r3); |
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180 | printk(" r4 = %8x r5 = %8x r6 = %8x r7 = %8x\n\r", |
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181 | ctx->register_r4, ctx->register_r5, |
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182 | ctx->register_r6, ctx->register_r7); |
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183 | printk(" r8 = %8x r9 = %8x r10 = %8x\n\r", |
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184 | ctx->register_r8, ctx->register_r9, ctx->register_r10); |
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185 | printk(" fp = %8x ip = %8x sp = %8x pc = %8x\n\r", |
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186 | ctx->register_fp, ctx->register_ip, |
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187 | ctx->register_sp, ctx->register_lr - 4); |
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188 | printk("----------------------------------------------------------\n\r"); |
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189 | #endif |
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190 | if (_ISR_Nest_level > 0) { |
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191 | /* |
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192 | * In this case we shall not delete the task interrupted as |
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193 | * it has nothing to do with the fault. We cannot return either |
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194 | * because the eip points to the faulty instruction so... |
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195 | */ |
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196 | printk("Exception while executing ISR!!!. System locked\n\r"); |
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197 | while(1); |
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198 | } |
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199 | else { |
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200 | printk("*********** FAULTY THREAD WILL BE DELETED **************\n\r"); |
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201 | rtems_task_delete(_Thread_Executing->Object.id); |
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202 | } |
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203 | } |
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204 | |
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205 | cpuExcHandlerType _currentExcHandler = _defaultExcHandler; |
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206 | |
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207 | extern void _Exception_Handler_Undef_Swi(void); |
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208 | extern void _Exception_Handler_Abort(void); |
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209 | extern void _exc_data_abort(void); |
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210 | |
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211 | |
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212 | |
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213 | /* FIXME: put comments here */ |
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214 | void rtems_exception_init_mngt(void) |
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215 | { |
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216 | ISR_Level level; |
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217 | |
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218 | _CPU_ISR_Disable(level); |
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219 | _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF, |
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220 | _Exception_Handler_Undef_Swi, |
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221 | NULL); |
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222 | |
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223 | _CPU_ISR_install_vector(ARM_EXCEPTION_SWI, |
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224 | _Exception_Handler_Undef_Swi, |
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225 | NULL); |
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226 | |
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227 | _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, |
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228 | _Exception_Handler_Abort, |
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229 | NULL); |
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230 | |
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231 | _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, |
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232 | _exc_data_abort, |
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233 | NULL); |
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234 | |
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235 | _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ, |
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236 | _Exception_Handler_Abort, |
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237 | NULL); |
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238 | |
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239 | _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, |
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240 | _Exception_Handler_Abort, |
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241 | NULL); |
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242 | |
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243 | _CPU_ISR_Enable(level); |
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244 | } |
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245 | |
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246 | #define INSN_MASK 0xc5 |
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247 | |
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248 | #define INSN_STM1 0x80 |
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249 | #define INSN_STM2 0x84 |
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250 | #define INSN_STR 0x40 |
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251 | #define INSN_STRB 0x44 |
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252 | |
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253 | #define INSN_LDM1 0x81 |
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254 | #define INSN_LDM23 0x85 |
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255 | #define INSN_LDR 0x41 |
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256 | #define INSN_LDRB 0x45 |
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257 | |
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258 | #define GET_RD(x) ((x & 0x0000f000) >> 12) |
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259 | #define GET_RN(x) ((x & 0x000f0000) >> 16) |
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260 | |
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261 | #define GET_U(x) ((x & 0x00800000) >> 23) |
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262 | #define GET_I(x) ((x & 0x02000000) >> 25) |
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263 | |
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264 | #define GET_REG(r, ctx) (((uint32_t *)ctx)[r]) |
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265 | #define SET_REG(r, ctx, v) (((uint32_t *)ctx)[r] = v) |
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266 | #define GET_OFFSET(insn) (insn & 0xfff) |
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267 | |
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