source: rtems/cpukit/score/cpu/arm/cpu.c @ 4f0b287

4.104.114.84.95
Last change on this file since 4f0b287 was 4f0b287, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 17, 2002 at 5:14:31 PM

2002-07-17 Jay Monkman <jtm@…>

  • rtems/score/cpu_asm.h: Enhanced to include register offsets.
  • Makefile.am: Install rtems/score/cpu_asm.h.
  • cpu.c: Significantly enhanced including the implementation of _CPU_ISR_Get_level.
  • cpu_asm.S: Improved behavior of context switch and interrupt dispatching.
  • rtems/score/arm.h: Improved the CPU model name determination.
  • rtems/score/cpu.h: Improved interrupt disable/enable functions.
  • Property mode set to 100644
File size: 6.7 KB
Line 
1/*
2 *  ARM CPU Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
6 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
7 *
8 *  Copyright (c) 2002 Advent Networks, Inc
9 *      Jay Monkman <jmonkman@adventnetworks.com>
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.OARcorp.com/rtems/license.html.
14 *
15 */
16
17#include <rtems/system.h>
18#include <rtems.h>
19#include <rtems/bspIo.h>
20#include <rtems/score/isr.h>
21#include <rtems/score/wkspace.h>
22#include <rtems/score/thread.h>
23#include <rtems/score/cpu.h>
24
25/*  _CPU_Initialize
26 *
27 *  This routine performs processor dependent initialization.
28 *
29 *  INPUT PARAMETERS:
30 *    cpu_table       - CPU table to initialize
31 *    thread_dispatch - address of ISR disptaching routine (unused)
32 *   
33 */
34
35void _CPU_Initialize(
36  rtems_cpu_table  *cpu_table,
37  void      (*thread_dispatch)      /* ignored on this CPU */
38)
39{
40    _CPU_Table = *cpu_table;
41}
42
43/*
44 *
45 *  _CPU_ISR_Get_level - returns the current interrupt level
46 */
47 
48unsigned32 _CPU_ISR_Get_level( void )
49{
50    unsigned32 reg;
51   
52    asm volatile ("mrs  %0, cpsr \n"           \
53                  "and  %0,  %0, #0xc0 \n"     \
54                  : "=r" (reg));
55   
56    return reg;
57}
58
59/*
60 *  _CPU_ISR_install_vector
61 *
62 *  This kernel routine installs the RTEMS handler for the
63 *  specified vector.
64 *
65 *  Input parameters:
66 *    vector      - interrupt vector number
67 *    new_handler - replacement ISR for this vector number
68 *    old_handler - pointer to store former ISR for this vector number
69 *
70 *  FIXME: This vector scheme should be changed to allow FIQ to be
71 *         handled better. I'd like to be able to put VectorTable
72 *         elsewhere - JTM
73 *
74 *
75 *  Output parameters:  NONE
76 *
77 */
78void _CPU_ISR_install_vector(
79  unsigned32  vector,
80  proc_ptr    new_handler,
81  proc_ptr   *old_handler
82)
83{
84    /* pointer on the redirection table in RAM */
85    long *VectorTable = (long *)(MAX_EXCEPTIONS * 4); 
86   
87    if (old_handler != NULL) {
88        old_handler = *(proc_ptr *)(VectorTable + vector);
89    }
90
91    *(VectorTable + vector) = (long)new_handler ;
92 
93}
94
95void _CPU_Context_Initialize(
96  Context_Control  *the_context,
97  unsigned32       *stack_base,
98  unsigned32        size,
99  unsigned32        new_level,
100  void             *entry_point,
101  boolean           is_fp
102)
103{
104    the_context->register_sp = ((unsigned32)(stack_base)) + (size) ;
105    the_context->register_pc = (entry_point);
106    the_context->register_cpsr = (new_level | 0x13);
107}
108
109/*PAGE
110 *
111 *  _CPU_Install_interrupt_stack
112 */
113
114void _CPU_Install_interrupt_stack( void )
115{
116/* FIXME: do something here */
117#if 0
118    extern unsigned long _fiq_stack;
119    extern unsigned long _fiq_stack_size;
120    extern unsigned long _irq_stack;
121    extern unsigned long _irq_stack_size;
122    extern unsigned long _abt_stack;
123    extern unsigned long _abt_stack_size;
124    unsigned long *ptr;
125    int i;
126
127    ptr = &_fiq_stack;
128    for (i = 0; i < ((int)&_fiq_stack_size/4); i++) {
129        ptr[i] = 0x13131313;
130    }
131
132    ptr = &_irq_stack;
133    for (i = 0; i < ((int)&_irq_stack_size/4); i++) {
134        ptr[i] = 0xf0f0f0f0;
135    }
136
137    ptr = &_abt_stack;
138    for (i = 0; i < ((int)&_abt_stack_size/4); i++) {
139        ptr[i] = 0x55555555;
140    }
141#endif
142}
143
144/*PAGE
145 *
146 *  _CPU_Thread_Idle_body
147 *
148 *  NOTES:
149 *
150 *  1. This is the same as the regular CPU independent algorithm.
151 *
152 *  2. If you implement this using a "halt", "idle", or "shutdown"
153 *     instruction, then don't forget to put it in an infinite loop.
154 *
155 *  3. Be warned. Some processors with onboard DMA have been known
156 *     to stop the DMA if the CPU were put in IDLE mode.  This might
157 *     also be a problem with other on-chip peripherals.  So use this
158 *     hook with caution.
159 */
160
161void _CPU_Thread_Idle_body( void )
162{
163
164    while(1); /* FIXME: finish this */
165    /* insert your "halt" instruction here */ ;
166}
167
168void _defaultExcHandler (CPU_Exception_frame *ctx)
169{
170    printk("\n\r");
171    printk("----------------------------------------------------------\n\r");
172    printk("Exception 0x%x caught at PC 0x%x by thread %d\n",
173           ctx->register_pc, ctx->register_lr - 4,
174           _Thread_Executing->Object.id);
175    printk("----------------------------------------------------------\n\r");
176    printk("Processor execution context at time of the fault was  :\n\r");
177    printk("----------------------------------------------------------\n\r");
178    printk(" r0  = %8x  r1  = %8x  r2  = %8x  r3  = %8x\n\r",
179           ctx->register_r0, ctx->register_r1, 
180           ctx->register_r2, ctx->register_r3);
181    printk(" r4  = %8x  r5  = %8x  r6  = %8x  r7  = %8x\n\r",
182           ctx->register_r4, ctx->register_r5, 
183           ctx->register_r6, ctx->register_r7);
184    printk(" r8  = %8x  r9  = %8x  r10 = %8x\n\r",
185           ctx->register_r8, ctx->register_r9, ctx->register_r10);
186    printk(" fp  = %8x  ip  = %8x  sp  = %8x  pc  = %8x\n\r",
187           ctx->register_fp, ctx->register_ip, 
188           ctx->register_sp, ctx->register_lr - 4);
189    printk("----------------------------------------------------------\n\r");
190   
191    if (_ISR_Nest_level > 0) {
192        /*
193         * In this case we shall not delete the task interrupted as
194         * it has nothing to do with the fault. We cannot return either
195         * because the eip points to the faulty instruction so...
196         */
197        printk("Exception while executing ISR!!!. System locked\n\r");
198        while(1);
199    }
200    else {
201        printk("*********** FAULTY THREAD WILL BE DELETED **************\n\r");
202        rtems_task_delete(_Thread_Executing->Object.id);
203    }
204}
205
206cpuExcHandlerType _currentExcHandler = _defaultExcHandler;
207
208extern void _Exception_Handler_Undef_Swi(); 
209extern void _Exception_Handler_Abort(); 
210/* FIXME: put comments here */
211void rtems_exception_init_mngt()
212{
213        ISR_Level level;
214     
215      _CPU_ISR_Disable(level);
216      _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,
217                              _Exception_Handler_Undef_Swi,
218                              NULL);
219 
220      _CPU_ISR_install_vector(ARM_EXCEPTION_SWI,
221                              _Exception_Handler_Undef_Swi,
222                              NULL);
223     
224      _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT,
225                              _Exception_Handler_Abort,
226                              NULL);
227     
228      _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT,
229                              _Exception_Handler_Abort,
230                              NULL);
231     
232      _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,       
233                              _Exception_Handler_Abort,
234                              NULL);
235     
236      _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, 
237                              _Exception_Handler_Abort,
238                              NULL);
239     
240      _CPU_ISR_Enable(level);
241}
242 
243
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