source: rtems/cpukit/score/cpu/arm/cpu.c @ 0acc9af

4.104.11
Last change on this file since 0acc9af was 0acc9af, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 27, 2010 at 3:01:19 PM

2010-03-27 Joel Sherrill <joel.sherrill@…>

  • arm_exc_abort.S, arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S, cpu.c, cpu_asm.S: Add include of config.h
  • Property mode set to 100644
File size: 2.8 KB
Line 
1/**
2 * @file
3 *
4 * ARM support code.
5 */
6
7/*
8 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
9 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
10 *
11 *  Copyright (c) 2002 Advent Networks, Inc
12 *      Jay Monkman <jmonkman@adventnetworks.com>
13 *
14 *  Copyright (c) 2007 Ray xu <rayx.cn@gmail.com>
15 *
16 *  Copyright (c) 2009 embedded brains GmbH
17 *
18 *  The license and distribution terms for this file may be
19 *  found in the file LICENSE in this distribution or at
20 *  http://www.rtems.com/license/LICENSE.
21 *
22 *  $Id$
23 */
24
25#ifdef HAVE_CONFIG_H
26#include "config.h"
27#endif
28
29#include <rtems/system.h>
30#include <rtems.h>
31#include <rtems/bspIo.h>
32#include <rtems/score/isr.h>
33#include <rtems/score/wkspace.h>
34#include <rtems/score/thread.h>
35#include <rtems/score/cpu.h>
36
37/*
38 * This variable can be used to change the running mode of the execution
39 * contexts.
40 */
41uint32_t arm_cpu_mode = 0x13;
42
43void _CPU_Context_Initialize(
44  Context_Control *the_context,
45  uint32_t *stack_base,
46  uint32_t size,
47  uint32_t new_level,
48  void *entry_point,
49  bool is_fp
50)
51{
52  the_context->register_sp = (uint32_t) stack_base + size ;
53  the_context->register_lr = (uint32_t) entry_point;
54  the_context->register_cpsr = new_level | arm_cpu_mode;
55}
56
57/* Preprocessor magic for stringification of x */
58#define _CPU_ISR_LEVEL_DO_STRINGOF( x) #x
59#define _CPU_ISR_LEVEL_STRINGOF( x) _CPU_ISR_LEVEL_DO_STRINGOF( x)
60
61void _CPU_ISR_Set_level( uint32_t level )
62{
63  uint32_t arm_switch_reg;
64
65  asm volatile (
66    ARM_SWITCH_TO_ARM
67    "mrs %[arm_switch_reg], cpsr\n"
68    "bic %[arm_switch_reg], #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n"
69    "orr %[arm_switch_reg], %[level]\n"
70    "msr cpsr, %0\n"
71    ARM_SWITCH_BACK
72    : [arm_switch_reg] "=&r" (arm_switch_reg)
73    : [level] "r" (level)
74  );
75}
76
77uint32_t _CPU_ISR_Get_level( void )
78{
79  ARM_SWITCH_REGISTERS;
80  uint32_t level;
81
82  asm volatile (
83    ARM_SWITCH_TO_ARM
84    "mrs %[level], cpsr\n"
85    "and %[level], #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n"
86    ARM_SWITCH_BACK
87    : [level] "=&r" (level) ARM_SWITCH_ADDITIONAL_OUTPUT
88  );
89
90  return level;
91}
92
93void _CPU_ISR_install_vector(
94  uint32_t vector,
95  proc_ptr new_handler,
96  proc_ptr *old_handler
97)
98{
99  /* Redirection table starts at the end of the vector table */
100  volatile uint32_t *table = (volatile uint32_t *) (MAX_EXCEPTIONS * 4);
101
102  uint32_t current_handler = table [vector];
103
104  /* The current handler is now the old one */
105  if (old_handler != NULL) {
106    *old_handler = (proc_ptr) current_handler;
107  }
108
109  /* Write only if necessary to avoid writes to a maybe read-only memory */
110  if (current_handler != (uint32_t) new_handler) {
111    table [vector] = (uint32_t) new_handler;
112  }
113}
114
115void _CPU_Install_interrupt_stack( void )
116{
117  /* This function is empty since the BSP must set up the interrupt stacks */
118}
119
120void _CPU_Initialize( void )
121{
122  /* Do nothing */
123}
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