[08330bf] | 1 | /* |
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| 2 | * ARM CPU Dependent Source |
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| 3 | * |
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| 4 | * |
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| 5 | * COPYRIGHT (c) 2000 Canon Research Centre France SA. |
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| 6 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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| 7 | * |
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[4f0b287] | 8 | * Copyright (c) 2002 Advent Networks, Inc |
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| 9 | * Jay Monkman <jmonkman@adventnetworks.com> |
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| 10 | * |
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[08330bf] | 11 | * The license and distribution terms for this file may be |
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| 12 | * found in the file LICENSE in this distribution or at |
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[57b8a7b6] | 13 | * http://www.rtems.com/license/LICENSE. |
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[08330bf] | 14 | * |
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| 15 | */ |
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| 16 | |
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| 17 | #include <rtems/system.h> |
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| 18 | #include <rtems.h> |
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[d56918c9] | 19 | #include <rtems/bspIo.h> |
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[08330bf] | 20 | #include <rtems/score/isr.h> |
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| 21 | #include <rtems/score/wkspace.h> |
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| 22 | #include <rtems/score/thread.h> |
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| 23 | #include <rtems/score/cpu.h> |
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| 24 | |
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| 25 | /* _CPU_Initialize |
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| 26 | * |
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| 27 | * This routine performs processor dependent initialization. |
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| 28 | * |
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| 29 | * INPUT PARAMETERS: |
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| 30 | * cpu_table - CPU table to initialize |
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[4f0b287] | 31 | * thread_dispatch - address of ISR disptaching routine (unused) |
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| 32 | * |
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[08330bf] | 33 | */ |
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| 34 | |
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| 35 | void _CPU_Initialize( |
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| 36 | rtems_cpu_table *cpu_table, |
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| 37 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 38 | ) |
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| 39 | { |
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| 40 | } |
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| 41 | |
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[4f0b287] | 42 | /* |
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[08330bf] | 43 | * |
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[4f0b287] | 44 | * _CPU_ISR_Get_level - returns the current interrupt level |
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[08330bf] | 45 | */ |
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| 46 | |
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[c346f33d] | 47 | uint32_t _CPU_ISR_Get_level( void ) |
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[08330bf] | 48 | { |
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[c346f33d] | 49 | uint32_t reg = 0; /* to avoid warning */ |
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[4f0b287] | 50 | |
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| 51 | asm volatile ("mrs %0, cpsr \n" \ |
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| 52 | "and %0, %0, #0xc0 \n" \ |
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[fa237002] | 53 | : "=r" (reg) \ |
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| 54 | : "0" (reg) ); |
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[4f0b287] | 55 | |
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| 56 | return reg; |
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[08330bf] | 57 | } |
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| 58 | |
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| 59 | /* |
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| 60 | * _CPU_ISR_install_vector |
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| 61 | * |
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| 62 | * This kernel routine installs the RTEMS handler for the |
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| 63 | * specified vector. |
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| 64 | * |
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| 65 | * Input parameters: |
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| 66 | * vector - interrupt vector number |
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| 67 | * new_handler - replacement ISR for this vector number |
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[4f0b287] | 68 | * old_handler - pointer to store former ISR for this vector number |
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| 69 | * |
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| 70 | * FIXME: This vector scheme should be changed to allow FIQ to be |
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| 71 | * handled better. I'd like to be able to put VectorTable |
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| 72 | * elsewhere - JTM |
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| 73 | * |
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[08330bf] | 74 | * |
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| 75 | * Output parameters: NONE |
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| 76 | * |
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| 77 | */ |
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| 78 | void _CPU_ISR_install_vector( |
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[c346f33d] | 79 | uint32_t vector, |
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[08330bf] | 80 | proc_ptr new_handler, |
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| 81 | proc_ptr *old_handler |
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| 82 | ) |
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| 83 | { |
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[4f0b287] | 84 | /* pointer on the redirection table in RAM */ |
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| 85 | long *VectorTable = (long *)(MAX_EXCEPTIONS * 4); |
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| 86 | |
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| 87 | if (old_handler != NULL) { |
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| 88 | old_handler = *(proc_ptr *)(VectorTable + vector); |
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| 89 | } |
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| 90 | |
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| 91 | *(VectorTable + vector) = (long)new_handler ; |
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[08330bf] | 92 | |
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| 93 | } |
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| 94 | |
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[4f0b287] | 95 | void _CPU_Context_Initialize( |
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| 96 | Context_Control *the_context, |
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[c346f33d] | 97 | uint32_t *stack_base, |
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| 98 | uint32_t size, |
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| 99 | uint32_t new_level, |
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[4f0b287] | 100 | void *entry_point, |
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| 101 | boolean is_fp |
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| 102 | ) |
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| 103 | { |
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[c346f33d] | 104 | the_context->register_sp = (uint32_t )stack_base + size ; |
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| 105 | the_context->register_lr = (uint32_t )entry_point; |
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[fa237002] | 106 | the_context->register_cpsr = new_level | 0x13; |
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[4f0b287] | 107 | } |
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| 108 | |
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[08330bf] | 109 | |
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[fa237002] | 110 | /* |
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| 111 | * _CPU_Install_interrupt_stack - this function is empty since the |
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| 112 | * BSP must set up the interrupt stacks. |
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[08330bf] | 113 | */ |
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| 114 | |
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[fa237002] | 115 | void _CPU_Install_interrupt_stack( void ) |
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[08330bf] | 116 | { |
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| 117 | } |
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| 118 | |
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| 119 | void _defaultExcHandler (CPU_Exception_frame *ctx) |
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| 120 | { |
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[4f0b287] | 121 | printk("\n\r"); |
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| 122 | printk("----------------------------------------------------------\n\r"); |
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[aed1db6c] | 123 | #if 1 |
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[4f0b287] | 124 | printk("Exception 0x%x caught at PC 0x%x by thread %d\n", |
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[aed1db6c] | 125 | ctx->register_ip, ctx->register_lr - 4, |
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[4f0b287] | 126 | _Thread_Executing->Object.id); |
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[fa237002] | 127 | #endif |
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[4f0b287] | 128 | printk("----------------------------------------------------------\n\r"); |
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| 129 | printk("Processor execution context at time of the fault was :\n\r"); |
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| 130 | printk("----------------------------------------------------------\n\r"); |
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[fa237002] | 131 | #if 0 |
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[4f0b287] | 132 | printk(" r0 = %8x r1 = %8x r2 = %8x r3 = %8x\n\r", |
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| 133 | ctx->register_r0, ctx->register_r1, |
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| 134 | ctx->register_r2, ctx->register_r3); |
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| 135 | printk(" r4 = %8x r5 = %8x r6 = %8x r7 = %8x\n\r", |
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| 136 | ctx->register_r4, ctx->register_r5, |
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| 137 | ctx->register_r6, ctx->register_r7); |
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| 138 | printk(" r8 = %8x r9 = %8x r10 = %8x\n\r", |
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| 139 | ctx->register_r8, ctx->register_r9, ctx->register_r10); |
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| 140 | printk(" fp = %8x ip = %8x sp = %8x pc = %8x\n\r", |
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| 141 | ctx->register_fp, ctx->register_ip, |
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| 142 | ctx->register_sp, ctx->register_lr - 4); |
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| 143 | printk("----------------------------------------------------------\n\r"); |
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[fa237002] | 144 | #endif |
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[4f0b287] | 145 | if (_ISR_Nest_level > 0) { |
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| 146 | /* |
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| 147 | * In this case we shall not delete the task interrupted as |
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| 148 | * it has nothing to do with the fault. We cannot return either |
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| 149 | * because the eip points to the faulty instruction so... |
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| 150 | */ |
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| 151 | printk("Exception while executing ISR!!!. System locked\n\r"); |
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| 152 | while(1); |
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| 153 | } |
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| 154 | else { |
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| 155 | printk("*********** FAULTY THREAD WILL BE DELETED **************\n\r"); |
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| 156 | rtems_task_delete(_Thread_Executing->Object.id); |
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| 157 | } |
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[08330bf] | 158 | } |
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| 159 | |
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| 160 | cpuExcHandlerType _currentExcHandler = _defaultExcHandler; |
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| 161 | |
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| 162 | extern void _Exception_Handler_Undef_Swi(); |
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| 163 | extern void _Exception_Handler_Abort(); |
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[fa237002] | 164 | extern void _exc_data_abort(); |
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[4f0b287] | 165 | /* FIXME: put comments here */ |
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[08330bf] | 166 | void rtems_exception_init_mngt() |
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| 167 | { |
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[4f0b287] | 168 | ISR_Level level; |
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[08330bf] | 169 | |
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| 170 | _CPU_ISR_Disable(level); |
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[4f0b287] | 171 | _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF, |
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| 172 | _Exception_Handler_Undef_Swi, |
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| 173 | NULL); |
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| 174 | |
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| 175 | _CPU_ISR_install_vector(ARM_EXCEPTION_SWI, |
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| 176 | _Exception_Handler_Undef_Swi, |
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| 177 | NULL); |
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| 178 | |
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| 179 | _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, |
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| 180 | _Exception_Handler_Abort, |
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| 181 | NULL); |
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| 182 | |
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| 183 | _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, |
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[fa237002] | 184 | _exc_data_abort, |
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[4f0b287] | 185 | NULL); |
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| 186 | |
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| 187 | _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ, |
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| 188 | _Exception_Handler_Abort, |
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| 189 | NULL); |
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| 190 | |
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| 191 | _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, |
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| 192 | _Exception_Handler_Abort, |
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| 193 | NULL); |
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| 194 | |
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[08330bf] | 195 | _CPU_ISR_Enable(level); |
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| 196 | } |
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| 197 | |
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[fa237002] | 198 | #define INSN_MASK 0xc5 |
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| 199 | |
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| 200 | #define INSN_STM1 0x80 |
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| 201 | #define INSN_STM2 0x84 |
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| 202 | #define INSN_STR 0x40 |
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| 203 | #define INSN_STRB 0x44 |
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| 204 | |
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| 205 | #define INSN_LDM1 0x81 |
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| 206 | #define INSN_LDM23 0x85 |
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| 207 | #define INSN_LDR 0x41 |
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| 208 | #define INSN_LDRB 0x45 |
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| 209 | |
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| 210 | #define GET_RD(x) ((x & 0x0000f000) >> 12) |
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| 211 | #define GET_RN(x) ((x & 0x000f0000) >> 16) |
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| 212 | |
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| 213 | #define GET_U(x) ((x & 0x00800000) >> 23) |
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| 214 | #define GET_I(x) ((x & 0x02000000) >> 25) |
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| 215 | |
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[c346f33d] | 216 | #define GET_REG(r, ctx) (((uint32_t *)ctx)[r]) |
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| 217 | #define SET_REG(r, ctx, v) (((uint32_t *)ctx)[r] = v) |
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[fa237002] | 218 | #define GET_OFFSET(insn) (insn & 0xfff) |
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| 219 | |
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