source: rtems/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c @ 2afb22b

5
Last change on this file since 2afb22b was 3e782743, checked in by Sebastian Huber <sebastian.huber@…>, on 07/04/17 at 12:15:03

arm: Fix ARMv7-M interrupt processing

Right after a "msr basepri_max, %[basepri]" instruction an interrupt
service may still take place (observed at least on Cortex-M7). However,
pendable service calls that are activated during this interrupt service
may be delayed until interrupts are enable again. The
_ARMV7M_Pendable_service_call() did not check that a thread dispatch is
allowed. Move this test from _ARMV7M_Interrupt_service_leave() to
_ARMV7M_Pendable_service_call().

Update #3060.
  • Property mode set to 100644
File size: 1.2 KB
Line 
1/**
2 *  @file
3 *
4 *  @brief ARMV7M Interrupt Service Enter and Leave
5 */
6
7/*
8 * Copyright (c) 2011, 2017 Sebastian Huber.  All rights reserved.
9 *
10 *  embedded brains GmbH
11 *  Dornierstr. 4
12 *  82178 Puchheim
13 *  Germany
14 *  <rtems@embedded-brains.de>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 */
20
21#ifdef HAVE_CONFIG_H
22  #include "config.h"
23#endif
24
25#include <rtems/score/armv7m.h>
26#include <rtems/score/isr.h>
27#include <rtems/score/threaddispatch.h>
28
29#ifdef ARM_MULTILIB_ARCH_V7M
30
31void _ARMV7M_Interrupt_service_enter( void )
32{
33  Per_CPU_Control *cpu_self = _Per_CPU_Get();
34
35  ++cpu_self->thread_dispatch_disable_level;
36  ++cpu_self->isr_nest_level;
37}
38
39void _ARMV7M_Interrupt_service_leave( void )
40{
41  Per_CPU_Control *cpu_self = _Per_CPU_Get();
42
43  --cpu_self->thread_dispatch_disable_level;
44  --cpu_self->isr_nest_level;
45
46  /*
47   * Optimistically activate a pendable service call if a thread dispatch is
48   * necessary.  The _ARMV7M_Pendable_service_call() will check that a thread
49   * dispatch is allowed.
50   */
51  if ( cpu_self->dispatch_necessary ) {
52    _ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVSET;
53  }
54}
55
56#endif /* ARM_MULTILIB_ARCH_V7M */
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