source: rtems/cpukit/score/cpu/arm/armv7m-isr-dispatch.c @ c499856

4.115
Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47

Change all references of rtems.com to rtems.org.

  • Property mode set to 100644
File size: 1.6 KB
Line 
1/**
2 * @file
3 *
4 * @brief ARMV7M ISR Dispatch
5 */
6
7/*
8 * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
9 *
10 *  embedded brains GmbH
11 *  Obere Lagerstr. 30
12 *  82178 Puchheim
13 *  Germany
14 *  <rtems@embedded-brains.de>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 */
20
21#ifdef HAVE_CONFIG_H
22  #include "config.h"
23#endif
24
25#include <rtems/score/armv7m.h>
26#include <rtems/score/percpu.h>
27
28#ifdef ARM_MULTILIB_ARCH_V7M
29
30static void __attribute__((naked)) _ARMV7M_Thread_dispatch( void )
31{
32  __asm__ volatile (
33    "bl _Thread_Dispatch\n"
34    /* FIXME: SVC, binutils bug */
35    ".short 0xdf00\n"
36    "nop\n"
37  );
38}
39
40void _ARMV7M_Pendable_service_call( void )
41{
42  _ISR_Nest_level = 1;
43  _ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR;
44  ARMV7M_Exception_frame *ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
45  --ef;
46  _ARMV7M_Set_PSP((uint32_t) ef);
47
48  /*
49   * According to "ARMv7-M Architecture Reference Manual" section B1.5.6
50   * "Exception entry behavior" the return address is half-word aligned.
51   */
52  ef->register_pc = (void *)
53    ((uintptr_t) _ARMV7M_Thread_dispatch & ~((uintptr_t) 1));
54
55  ef->register_xpsr = 0x01000000U;
56}
57
58void _ARMV7M_Supervisor_call( void )
59{
60  ARMV7M_Exception_frame *ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
61  ++ef;
62  _ARMV7M_Set_PSP((uint32_t) ef);
63  _ISR_Nest_level = 0;
64  RTEMS_COMPILER_MEMORY_BARRIER();
65  if ( _Thread_Dispatch_necessary ) {
66    _ARMV7M_Pendable_service_call();
67  }
68}
69
70#endif /* ARM_MULTILIB_ARCH_V7M */
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