source: rtems/cpukit/score/cpu/arm/armv7m-isr-dispatch.c @ c0443b4c

5
Last change on this file since c0443b4c was 3e782743, checked in by Sebastian Huber <sebastian.huber@…>, on 07/04/17 at 12:15:03

arm: Fix ARMv7-M interrupt processing

Right after a "msr basepri_max, %[basepri]" instruction an interrupt
service may still take place (observed at least on Cortex-M7). However,
pendable service calls that are activated during this interrupt service
may be delayed until interrupts are enable again. The
_ARMV7M_Pendable_service_call() did not check that a thread dispatch is
allowed. Move this test from _ARMV7M_Interrupt_service_leave() to
_ARMV7M_Pendable_service_call().

Update #3060.

  • Property mode set to 100644
File size: 2.3 KB
Line 
1/**
2 * @file
3 *
4 * @brief ARMV7M ISR Dispatch
5 */
6
7/*
8 * Copyright (c) 2011, 2017 Sebastian Huber.  All rights reserved.
9 *
10 *  embedded brains GmbH
11 *  Dornierstr. 4
12 *  82178 Puchheim
13 *  Germany
14 *  <rtems@embedded-brains.de>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 */
20
21#ifdef HAVE_CONFIG_H
22  #include "config.h"
23#endif
24
25#include <rtems/score/armv7m.h>
26#include <rtems/score/percpu.h>
27
28#ifdef ARM_MULTILIB_ARCH_V7M
29
30static void __attribute__((naked)) _ARMV7M_Thread_dispatch( void )
31{
32  __asm__ volatile (
33    "bl _Thread_Dispatch\n"
34    /* FIXME: SVC, binutils bug */
35    ".short 0xdf00\n"
36    "nop\n"
37  );
38}
39
40static void _ARMV7M_Trigger_lazy_floating_point_context_save( void )
41{
42#ifdef ARM_MULTILIB_VFP
43  __asm__ volatile (
44    "vmov.f32 s0, s0\n"
45  );
46#endif
47}
48
49void _ARMV7M_Pendable_service_call( void )
50{
51  Per_CPU_Control *cpu_self = _Per_CPU_Get();
52
53  /*
54   * We must check here if a thread dispatch is allowed.  Right after a
55   * "msr basepri_max, %[basepri]" instruction an interrupt service may still
56   * take place.  However, pendable service calls that are activated during
57   * this interrupt service may be delayed until interrupts are enable again.
58   */
59  if (
60    ( cpu_self->isr_nest_level | cpu_self->thread_dispatch_disable_level ) == 0
61  ) {
62    ARMV7M_Exception_frame *ef;
63
64    cpu_self->isr_nest_level = 1;
65
66    _ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR;
67    _ARMV7M_Trigger_lazy_floating_point_context_save();
68
69    ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
70    --ef;
71    _ARMV7M_Set_PSP( (uint32_t) ef );
72
73    /*
74     * According to "ARMv7-M Architecture Reference Manual" section B1.5.6
75     * "Exception entry behavior" the return address is half-word aligned.
76     */
77    ef->register_pc = (void *)
78      ((uintptr_t) _ARMV7M_Thread_dispatch & ~((uintptr_t) 1));
79
80    ef->register_xpsr = 0x01000000U;
81  }
82}
83
84void _ARMV7M_Supervisor_call( void )
85{
86  Per_CPU_Control *cpu_self = _Per_CPU_Get();
87  ARMV7M_Exception_frame *ef;
88
89  _ARMV7M_Trigger_lazy_floating_point_context_save();
90
91  ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
92  ++ef;
93  _ARMV7M_Set_PSP( (uint32_t) ef );
94
95  cpu_self->isr_nest_level = 0;
96
97  if ( cpu_self->dispatch_necessary ) {
98    _ARMV7M_Pendable_service_call();
99  }
100}
101
102#endif /* ARM_MULTILIB_ARCH_V7M */
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