1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief ARMV7M ISR Dispatch |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2011, 2017 Sebastian Huber. All rights reserved. |
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9 | * |
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10 | * embedded brains GmbH |
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11 | * Dornierstr. 4 |
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12 | * 82178 Puchheim |
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13 | * Germany |
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14 | * <rtems@embedded-brains.de> |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.org/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #ifdef HAVE_CONFIG_H |
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22 | #include "config.h" |
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23 | #endif |
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24 | |
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25 | #include <rtems/score/armv7m.h> |
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26 | #include <rtems/score/percpu.h> |
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27 | |
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28 | #ifdef ARM_MULTILIB_ARCH_V7M |
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29 | |
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30 | static void __attribute__((naked)) _ARMV7M_Thread_dispatch( void ) |
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31 | { |
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32 | __asm__ volatile ( |
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33 | "bl _Thread_Dispatch\n" |
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34 | /* FIXME: SVC, binutils bug */ |
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35 | ".short 0xdf00\n" |
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36 | "nop\n" |
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37 | ); |
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38 | } |
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39 | |
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40 | static void _ARMV7M_Trigger_lazy_floating_point_context_save( void ) |
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41 | { |
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42 | #ifdef ARM_MULTILIB_VFP |
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43 | __asm__ volatile ( |
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44 | "vmov.f32 s0, s0\n" |
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45 | ); |
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46 | #endif |
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47 | } |
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48 | |
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49 | void _ARMV7M_Pendable_service_call( void ) |
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50 | { |
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51 | Per_CPU_Control *cpu_self = _Per_CPU_Get(); |
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52 | |
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53 | /* |
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54 | * We must check here if a thread dispatch is allowed. Right after a |
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55 | * "msr basepri_max, %[basepri]" instruction an interrupt service may still |
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56 | * take place. However, pendable service calls that are activated during |
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57 | * this interrupt service may be delayed until interrupts are enable again. |
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58 | */ |
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59 | if ( |
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60 | ( cpu_self->isr_nest_level | cpu_self->thread_dispatch_disable_level ) == 0 |
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61 | ) { |
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62 | ARMV7M_Exception_frame *ef; |
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63 | |
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64 | cpu_self->isr_nest_level = 1; |
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65 | |
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66 | _ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR; |
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67 | _ARMV7M_Trigger_lazy_floating_point_context_save(); |
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68 | |
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69 | ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP(); |
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70 | --ef; |
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71 | _ARMV7M_Set_PSP( (uint32_t) ef ); |
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72 | |
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73 | /* |
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74 | * According to "ARMv7-M Architecture Reference Manual" section B1.5.6 |
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75 | * "Exception entry behavior" the return address is half-word aligned. |
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76 | */ |
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77 | ef->register_pc = (void *) |
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78 | ((uintptr_t) _ARMV7M_Thread_dispatch & ~((uintptr_t) 1)); |
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79 | |
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80 | ef->register_xpsr = 0x01000000U; |
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81 | } |
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82 | } |
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83 | |
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84 | void _ARMV7M_Supervisor_call( void ) |
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85 | { |
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86 | Per_CPU_Control *cpu_self = _Per_CPU_Get(); |
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87 | ARMV7M_Exception_frame *ef; |
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88 | |
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89 | _ARMV7M_Trigger_lazy_floating_point_context_save(); |
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90 | |
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91 | ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP(); |
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92 | ++ef; |
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93 | _ARMV7M_Set_PSP( (uint32_t) ef ); |
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94 | |
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95 | cpu_self->isr_nest_level = 0; |
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96 | |
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97 | if ( cpu_self->dispatch_necessary ) { |
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98 | _ARMV7M_Pendable_service_call(); |
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99 | } |
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100 | } |
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101 | |
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102 | #endif /* ARM_MULTILIB_ARCH_V7M */ |
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