source: rtems/cpukit/score/cpu/arm/armv7m-exception-handler-set.c @ eb142fee

5
Last change on this file since eb142fee was 819a6b35, checked in by Sebastian Huber <sebastian.huber@…>, on 01/14/16 at 07:07:06

arm: Honor cache for Cortex-M7 support

  • Property mode set to 100644
File size: 1.0 KB
Line 
1/**
2 *  @file
3 *
4 *  @brief ARMV7M Set Exception Handler
5 */
6
7/*
8 * Copyright (c) 2011, 2016 Sebastian Huber.  All rights reserved.
9 *
10 *  embedded brains GmbH
11 *  Dornierstr. 4
12 *  82178 Puchheim
13 *  Germany
14 *  <rtems@embedded-brains.de>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 */
20
21#ifdef HAVE_CONFIG_H
22  #include "config.h"
23#endif
24
25#include <rtems/score/armv7m.h>
26#include <rtems/rtems/cache.h>
27
28#ifdef ARM_MULTILIB_ARCH_V7M
29
30void _ARMV7M_Set_exception_handler(
31  int index,
32  ARMV7M_Exception_handler handler
33)
34{
35  if ( _ARMV7M_SCB->vtor [index] != handler ) {
36    _ARMV7M_SCB->vtor [index] = handler;
37    rtems_cache_flush_multiple_data_lines(
38      &_ARMV7M_SCB->vtor [index],
39      sizeof(_ARMV7M_SCB->vtor [index])
40    );
41    rtems_cache_invalidate_multiple_instruction_lines(
42      &_ARMV7M_SCB->vtor [index],
43      sizeof(_ARMV7M_SCB->vtor [index])
44    );
45  }
46}
47
48#endif /* ARM_MULTILIB_ARCH_V7M */
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