source: rtems/cpukit/score/cpu/arm/armv7m-exception-default.c @ a6c5a7e0

4.115
Last change on this file since a6c5a7e0 was 8ae37323, checked in by Sebastian Huber <sebastian.huber@…>, on 08/10/14 at 16:36:30

arm: Add support for FPv4-SP floating point unit

This floating point unit is available in Cortex-M4 processors and
defined by ARMv7-M. This adds basic support for other VFP-D16 variants.

  • Property mode set to 100644
File size: 2.0 KB
Line 
1/*
2 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Obere Lagerstr. 30
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#ifdef HAVE_CONFIG_H
16  #include "config.h"
17#endif
18
19#include <rtems/score/armv7m.h>
20
21#ifdef ARM_MULTILIB_ARCH_V7M
22
23void __attribute__((naked)) _ARMV7M_Exception_default( void )
24{
25  __asm__ volatile (
26    "sub sp, %[cpufsz]\n"
27    "stm sp, {r0-r12}\n"
28    "mov r2, lr\n"
29    "mrs r1, msp\n"
30    "mrs r0, psp\n"
31    "cmn r2, #3\n"
32    "itt ne\n"
33    "movne r0, r1\n"
34    "addne r0, %[cpufsz]\n"
35    "add r2, r0, %[v7mlroff]\n"
36    "add r1, sp, %[cpulroff]\n"
37    "ldm r2, {r3-r5}\n"
38    "stm r1, {r3-r5}\n"
39    "mrs r1, ipsr\n"
40    "str r1, [sp, %[cpuvecoff]]\n"
41
42    /* Argument for high level handler */
43    "mov r0, sp\n"
44
45    /* Clear VFP context pointer */
46    "add r3, sp, %[cpuvfpoff]\n"
47    "mov r1, #0\n"
48    "str r1, [r3]\n"
49
50#ifdef ARM_MULTILIB_VFP
51    /* Ensure that the FPU is enabled */
52    "ldr r4, =%[cpacr]\n"
53    "tst r4, #(0xf << 20)\n"
54    "bne 1f\n"
55
56    /* Save VFP context */
57    "sub sp, %[vfpsz]\n"
58    "add r4, sp, #4\n"
59    "bic r4, r4, #7\n"
60    "str r4, [r3]\n"
61    "vmrs r2, FPSCR\n"
62    "stmia r4!, {r1-r2}\n"
63    "vstmia r4!, {d0-d15}\n"
64    "mov r1, #0\n"
65    "mov r2, #0\n"
66    "adds r3, r4, #128\n"
67    "2:\n"
68    "stmia r4!, {r1-r2}\n"
69    "cmp r4, r3\n"
70    "bne 2b\n"
71    "1:\n"
72#endif
73
74    "b _ARM_Exception_default\n"
75    :
76    : [cpufsz] "i" (sizeof(CPU_Exception_frame)),
77      [v7mfsz] "i" (sizeof(ARMV7M_Exception_frame)),
78      [cpulroff] "i" (offsetof(CPU_Exception_frame, register_lr)),
79      [v7mlroff] "i" (offsetof(ARMV7M_Exception_frame, register_lr)),
80      [cpuvecoff] "J" (offsetof(CPU_Exception_frame, vector)),
81      [cpuvfpoff] "i" (ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET),
82      [cpacr] "i" (ARMV7M_CPACR),
83      [vfpsz] "i" (ARM_VFP_CONTEXT_SIZE)
84  );
85}
86
87#endif /* ARM_MULTILIB_ARCH_V7M */
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