1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief ARM7M CPU Context Switch |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2011 Sebastian Huber. All rights reserved. |
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9 | * |
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10 | * embedded brains GmbH |
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11 | * Obere Lagerstr. 30 |
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12 | * 82178 Puchheim |
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13 | * Germany |
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14 | * <rtems@embedded-brains.de> |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.org/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #ifdef HAVE_CONFIG_H |
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22 | #include "config.h" |
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23 | #endif |
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24 | |
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25 | #include <rtems/score/armv7m.h> |
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26 | #include <rtems/score/percpu.h> |
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27 | |
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28 | #ifdef ARM_MULTILIB_ARCH_V7M |
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29 | |
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30 | void __attribute__((naked)) _CPU_Context_switch( |
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31 | Context_Control *executing, |
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32 | Context_Control *heir |
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33 | ) |
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34 | { |
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35 | __asm__ volatile ( |
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36 | "movw r2, #:lower16:_Per_CPU_Information\n" |
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37 | "movt r2, #:upper16:_Per_CPU_Information\n" |
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38 | "ldr r3, [r2, %[isrpcpuoff]]\n" |
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39 | "stm r0, {r4-r11, lr}\n" |
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40 | "str sp, [r0, %[spctxoff]]\n" |
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41 | "str r3, [r0, %[isrctxoff]]\n" |
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42 | "ldr r3, [r1, %[isrctxoff]]\n" |
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43 | "ldr sp, [r1, %[spctxoff]]\n" |
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44 | "ldm r1, {r4-r11, lr}\n" |
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45 | "str r3, [r2, %[isrpcpuoff]]\n" |
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46 | "bx lr\n" |
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47 | : |
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48 | : [spctxoff] "J" (offsetof(Context_Control, register_sp)), |
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49 | [isrctxoff] "J" (offsetof(Context_Control, isr_nest_level)), |
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50 | [isrpcpuoff] "J" (offsetof(Per_CPU_Control, isr_nest_level)) |
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51 | ); |
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52 | } |
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53 | |
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54 | #endif /* ARM_MULTILIB_ARCH_V7M */ |
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