source: rtems/cpukit/score/cpu/arm/armv4-exception-default.S @ cfd8d7a

4.115
Last change on this file since cfd8d7a was cfd8d7a, checked in by Sebastian Huber <sebastian.huber@…>, on May 8, 2013 at 7:30:31 AM

arm: Support VFP-D32 and Neon

  • Property mode set to 100644
File size: 2.7 KB
Line 
1/*
2 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Obere Lagerstr. 30
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 */
14
15#ifdef HAVE_CONFIG_H
16  #include "config.h"
17#endif
18
19#include <rtems/asm.h>
20#include <rtems/system.h>
21
22#ifdef ARM_MULTILIB_ARCH_V4
23
24#define MORE_CONTEXT_SIZE \
25  (ARM_EXCEPTION_FRAME_SIZE - ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET)
26
27.extern _ARM_Exception_default
28
29.globl _ARMV4_Exception_undef_default
30.globl _ARMV4_Exception_swi_default
31.globl _ARMV4_Exception_data_abort_default
32.globl _ARMV4_Exception_pref_abort_default
33.globl _ARMV4_Exception_reserved_default
34.globl _ARMV4_Exception_irq_default
35.globl _ARMV4_Exception_fiq_default
36
37.section ".text"
38
39.arm
40
41_ARMV4_Exception_undef_default:
42
43        /* Save context and load vector */
44        sub     sp, #MORE_CONTEXT_SIZE
45        stmdb   sp!, {r0-r12}
46        mov     r4, #1
47
48        b       save_more_context
49
50_ARMV4_Exception_swi_default:
51
52        /* Save context and load vector */
53        sub     sp, #MORE_CONTEXT_SIZE
54        stmdb   sp!, {r0-r12}
55        mov     r4, #2
56
57        b       save_more_context
58
59_ARMV4_Exception_pref_abort_default:
60
61        /* Save context and load vector */
62        sub     sp, #MORE_CONTEXT_SIZE
63        stmdb   sp!, {r0-r12}
64        mov     r4, #3
65
66        b       save_more_context
67
68_ARMV4_Exception_data_abort_default:
69
70        /* Save context and load vector */
71        sub     sp, #MORE_CONTEXT_SIZE
72        stmdb   sp!, {r0-r12}
73        mov     r4, #4
74
75_ARMV4_Exception_reserved_default:
76
77        /* Save context and load vector */
78        sub     sp, #MORE_CONTEXT_SIZE
79        stmdb   sp!, {r0-r12}
80        mov     r4, #5
81
82_ARMV4_Exception_irq_default:
83
84        /* Save context and load vector */
85        sub     sp, #MORE_CONTEXT_SIZE
86        stmdb   sp!, {r0-r12}
87        mov     r4, #6
88
89_ARMV4_Exception_fiq_default:
90
91        /* Save context and load vector */
92        sub     sp, #MORE_CONTEXT_SIZE
93        stmdb   sp!, {r0-r12}
94        mov     r4, #7
95
96save_more_context:
97
98        /* Save more context */
99        mov     r2, lr
100        mrs     r3, spsr
101        mrs     r7, cpsr
102        orr     r5, r3, #ARM_PSR_I
103        bic     r5, #ARM_PSR_T
104        msr     cpsr, r5
105        sub     r0, sp, #ARM_EXCEPTION_FRAME_SIZE
106        mov     r1, lr
107        msr     cpsr, r7
108        mov     r5, #0
109        add     r6, sp, #ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET
110        stm     r6, {r0-r5}
111
112        /* Argument for high level handler */
113        mov     r0, sp
114
115#ifdef ARM_MULTILIB_VFP_D32
116        /* Ensure that the FPU is enabled */
117        vmrs    r1, FPEXC
118        tst     r1, #(1 << 30)
119        beq     fpu_save_done
120
121        add     r3, sp, #ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET
122        sub     sp, #(ARM_VFP_CONTEXT_SIZE + 4)
123        add     r4, sp, #4
124        bic     r4, r4, #7
125        str     r4, [r3]
126        vmrs    r2, FPSCR
127        stmia   r4!, {r1-r2}
128        vstmia  r4!, {d0-d15}
129        vstmia  r4!, {d16-d31}
130
131fpu_save_done:
132#endif
133
134        /* Call high level handler */
135        SWITCH_FROM_ARM_TO_THUMB        r1
136        bl      _ARM_Exception_default
137
138        /* Just in case */
139twiddle:
140        b       twiddle
141
142#endif /* ARM_MULTILIB_ARCH_V4 */
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