source: rtems/cpukit/score/cpu/arm/armv4-exception-default.S @ 8df0e91

4.115
Last change on this file since 8df0e91 was 13cf952, checked in by Sebastian Huber <sebastian.huber@…>, on 01/04/13 at 14:47:34

arm: Add and use default exception handler

Add and use _ARMV4_Exception_undef_default(),
_ARMV4_Exception_swi_default(), _ARMV4_Exception_data_abort_default(),
_ARMV4_Exception_pref_abort_default(),
_ARMV4_Exception_reserved_default(), _ARMV4_Exception_irq_default(), and
_ARMV4_Exception_fiq_default().
  • Property mode set to 100644
File size: 2.0 KB
Line 
1/*
2 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Obere Lagerstr. 30
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 */
14
15#ifdef HAVE_CONFIG_H
16  #include "config.h"
17#endif
18
19#include <rtems/asm.h>
20#include <rtems/system.h>
21
22#ifdef ARM_MULTILIB_ARCH_V4
23
24.extern _ARM_Exception_default
25
26.globl _ARMV4_Exception_undef_default
27.globl _ARMV4_Exception_swi_default
28.globl _ARMV4_Exception_data_abort_default
29.globl _ARMV4_Exception_pref_abort_default
30.globl _ARMV4_Exception_reserved_default
31.globl _ARMV4_Exception_irq_default
32.globl _ARMV4_Exception_fiq_default
33
34.section ".text"
35
36.arm
37
38_ARMV4_Exception_undef_default:
39
40        /* Save context and load vector */
41        sub     sp, #20
42        stmdb   sp!, {r0-r12}
43        mov     r4, #1
44
45        b       save_more_context
46
47_ARMV4_Exception_swi_default:
48
49        /* Save context and load vector */
50        sub     sp, #20
51        stmdb   sp!, {r0-r12}
52        mov     r4, #2
53
54        b       save_more_context
55
56_ARMV4_Exception_pref_abort_default:
57
58        /* Save context and load vector */
59        sub     sp, #20
60        stmdb   sp!, {r0-r12}
61        mov     r4, #3
62
63        b       save_more_context
64
65_ARMV4_Exception_data_abort_default:
66
67        /* Save context and load vector */
68        sub     sp, #20
69        stmdb   sp!, {r0-r12}
70        mov     r4, #4
71
72_ARMV4_Exception_reserved_default:
73
74        /* Save context and load vector */
75        sub     sp, #20
76        stmdb   sp!, {r0-r12}
77        mov     r4, #5
78
79_ARMV4_Exception_irq_default:
80
81        /* Save context and load vector */
82        sub     sp, #20
83        stmdb   sp!, {r0-r12}
84        mov     r4, #6
85
86_ARMV4_Exception_fiq_default:
87
88        /* Save context and load vector */
89        sub     sp, #20
90        stmdb   sp!, {r0-r12}
91        mov     r4, #7
92
93save_more_context:
94
95        /* Save more context */
96        mov     r2, lr
97        mrs     r3, spsr
98        mrs     r7, cpsr
99        orr     r5, r3, #ARM_PSR_I
100        bic     r5, #ARM_PSR_T
101        msr     cpsr, r5
102        mov     r0, sp
103        mov     r1, lr
104        msr     cpsr, r7
105        add     r5, sp, #72
106        stmdb   r5!, {r0-r4}
107
108        /* Call high level handler */
109        mov     r0, sp
110        SWITCH_FROM_ARM_TO_THUMB        r1
111        bl      _ARM_Exception_default
112
113        /* Just in case */
114twiddle:
115        b       twiddle
116
117#endif /* ARM_MULTILIB_ARCH_V4 */
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