1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup ScoreCPU |
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5 | * |
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6 | * @brief ARM interrupt exception prologue and epilogue. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009-2014 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | /* |
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24 | * The upper EXCHANGE_SIZE bytes of the INT stack area are used for data |
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25 | * exchange between INT and SVC mode. Below of this is the actual INT stack. |
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26 | * The exchange area is only accessed if INT is disabled. |
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27 | */ |
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28 | |
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29 | #ifdef HAVE_CONFIG_H |
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30 | #include "config.h" |
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31 | #endif |
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32 | |
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33 | #include <rtems/asm.h> |
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34 | |
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35 | #ifdef ARM_MULTILIB_ARCH_V4 |
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36 | |
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37 | #define EXCHANGE_LR r4 |
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38 | #define EXCHANGE_SPSR r5 |
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39 | #define EXCHANGE_CPSR r6 |
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40 | #define EXCHANGE_INT_SP r8 |
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41 | |
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42 | #define EXCHANGE_LIST {EXCHANGE_LR, EXCHANGE_SPSR, EXCHANGE_CPSR, EXCHANGE_INT_SP} |
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43 | #define EXCHANGE_SIZE 16 |
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44 | |
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45 | #define SELF_CPU_CONTROL r7 |
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46 | #define SP_OF_INTERRUPTED_CONTEXT r9 |
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47 | |
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48 | #define CONTEXT_LIST {r0, r1, r2, r3, EXCHANGE_LR, EXCHANGE_SPSR, SELF_CPU_CONTROL, r12} |
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49 | #define CONTEXT_SIZE 32 |
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50 | |
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51 | .arm |
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52 | .globl _ARMV4_Exception_interrupt |
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53 | _ARMV4_Exception_interrupt: |
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54 | |
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55 | /* Save exchange registers to exchange area */ |
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56 | stmdb sp, EXCHANGE_LIST |
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57 | |
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58 | /* Set exchange registers */ |
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59 | mov EXCHANGE_LR, lr |
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60 | mrs EXCHANGE_SPSR, SPSR |
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61 | mrs EXCHANGE_CPSR, CPSR |
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62 | sub EXCHANGE_INT_SP, sp, #EXCHANGE_SIZE |
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63 | |
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64 | /* Switch to SVC mode */ |
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65 | orr EXCHANGE_CPSR, EXCHANGE_CPSR, #0x1 |
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66 | msr CPSR_c, EXCHANGE_CPSR |
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67 | |
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68 | /* |
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69 | * Save context. We save the link register separately because it has |
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70 | * to be restored in SVC mode. The other registers can be restored in |
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71 | * INT mode. Ensure that stack remains 8 byte aligned. Use register |
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72 | * necessary for the stack alignment for the stack pointer of the |
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73 | * interrupted context. |
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74 | */ |
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75 | stmdb sp!, CONTEXT_LIST |
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76 | stmdb sp!, {SP_OF_INTERRUPTED_CONTEXT, lr} |
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77 | |
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78 | #ifdef ARM_MULTILIB_VFP |
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79 | /* Save VFP context */ |
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80 | vmrs r0, FPSCR |
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81 | vstmdb sp!, {d0-d7} |
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82 | #ifdef ARM_MULTILIB_VFP_D32 |
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83 | vstmdb sp!, {d16-d31} |
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84 | #endif |
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85 | stmdb sp!, {r0, r1} |
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86 | #endif /* ARM_MULTILIB_VFP */ |
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87 | |
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88 | /* Get per-CPU control of current processor */ |
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89 | GET_SELF_CPU_CONTROL SELF_CPU_CONTROL, r1 |
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90 | |
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91 | /* Remember INT stack pointer */ |
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92 | mov r1, EXCHANGE_INT_SP |
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93 | |
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94 | /* Restore exchange registers from exchange area */ |
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95 | ldmia r1, EXCHANGE_LIST |
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96 | |
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97 | /* Get interrupt nest level */ |
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98 | ldr r2, [SELF_CPU_CONTROL, #PER_CPU_ISR_NEST_LEVEL] |
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99 | |
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100 | /* Switch stack if necessary and save original stack pointer */ |
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101 | mov SP_OF_INTERRUPTED_CONTEXT, sp |
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102 | cmp r2, #0 |
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103 | moveq sp, r1 |
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104 | |
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105 | /* Switch to THUMB instructions if necessary */ |
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106 | SWITCH_FROM_ARM_TO_THUMB r1 |
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107 | |
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108 | /* Increment interrupt nest and thread dispatch disable level */ |
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109 | ldr r3, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL] |
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110 | add r2, #1 |
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111 | add r3, #1 |
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112 | str r2, [SELF_CPU_CONTROL, #PER_CPU_ISR_NEST_LEVEL] |
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113 | str r3, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL] |
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114 | |
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115 | #ifdef RTEMS_PROFILING |
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116 | cmp r2, #1 |
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117 | bne profiling_entry_done |
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118 | bl _CPU_Counter_read |
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119 | push {r0, r1} |
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120 | profiling_entry_done: |
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121 | #endif |
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122 | |
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123 | /* Call BSP dependent interrupt dispatcher */ |
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124 | bl bsp_interrupt_dispatch |
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125 | |
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126 | /* Decrement interrupt nest and thread dispatch disable level */ |
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127 | ldr r2, [SELF_CPU_CONTROL, #PER_CPU_ISR_NEST_LEVEL] |
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128 | ldr r3, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL] |
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129 | sub r2, #1 |
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130 | sub r3, #1 |
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131 | str r2, [SELF_CPU_CONTROL, #PER_CPU_ISR_NEST_LEVEL] |
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132 | str r3, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL] |
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133 | |
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134 | #ifdef RTEMS_PROFILING |
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135 | cmp r2, #0 |
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136 | bne profiling_exit_done |
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137 | bl _CPU_Counter_read |
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138 | pop {r1, r3} |
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139 | mov r2, r0 |
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140 | mov r0, SELF_CPU_CONTROL |
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141 | bl _Profiling_Outer_most_interrupt_entry_and_exit |
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142 | ldr r3, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL] |
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143 | profiling_exit_done: |
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144 | #endif |
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145 | |
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146 | /* Restore stack pointer */ |
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147 | mov sp, SP_OF_INTERRUPTED_CONTEXT |
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148 | |
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149 | /* Check thread dispatch disable level */ |
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150 | cmp r3, #0 |
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151 | bne thread_dispatch_done |
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152 | |
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153 | /* Check context switch necessary */ |
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154 | ldrb r1, [SELF_CPU_CONTROL, #PER_CPU_DISPATCH_NEEDED] |
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155 | cmp r1, #0 |
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156 | beq thread_dispatch_done |
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157 | |
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158 | /* This aligns thread_dispatch_done on a 4 byte boundary */ |
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159 | #ifdef __thumb__ |
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160 | nop |
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161 | #endif /* __thumb__ */ |
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162 | |
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163 | /* Thread dispatch */ |
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164 | bl _Thread_Dispatch |
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165 | |
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166 | thread_dispatch_done: |
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167 | |
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168 | /* Switch to ARM instructions if necessary */ |
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169 | SWITCH_FROM_THUMB_TO_ARM |
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170 | |
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171 | #ifdef ARM_MULTILIB_VFP |
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172 | /* Restore VFP context */ |
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173 | ldmia sp!, {r0, r1} |
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174 | #ifdef ARM_MULTILIB_VFP_D32 |
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175 | vldmia sp!, {d16-d31} |
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176 | #endif |
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177 | vldmia sp!, {d0-d7} |
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178 | vmsr FPSCR, r0 |
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179 | #endif /* ARM_MULTILIB_VFP */ |
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180 | |
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181 | /* Restore SP_OF_INTERRUPTED_CONTEXT register and link register */ |
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182 | ldmia sp!, {SP_OF_INTERRUPTED_CONTEXT, lr} |
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183 | |
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184 | /* |
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185 | * XXX: Remember and restore stack pointer. The data on the stack is |
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186 | * still in use. So the stack is now in an inconsistent state. The |
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187 | * FIQ handler implementation must not use this area. |
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188 | */ |
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189 | mov r0, sp |
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190 | add sp, #CONTEXT_SIZE |
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191 | |
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192 | /* Get INT mode program status register */ |
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193 | mrs r1, CPSR |
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194 | bic r1, r1, #0x1 |
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195 | |
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196 | /* Switch to INT mode */ |
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197 | msr CPSR_c, r1 |
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198 | |
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199 | /* Save EXCHANGE_LR and EXCHANGE_SPSR registers to exchange area */ |
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200 | stmdb sp!, {EXCHANGE_LR, EXCHANGE_SPSR} |
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201 | |
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202 | /* Restore context */ |
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203 | ldmia r0, CONTEXT_LIST |
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204 | |
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205 | /* Set return address and program status */ |
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206 | mov lr, EXCHANGE_LR |
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207 | msr SPSR_fsxc, EXCHANGE_SPSR |
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208 | |
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209 | /* Restore EXCHANGE_LR and EXCHANGE_SPSR registers from exchange area */ |
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210 | ldmia sp!, {EXCHANGE_LR, EXCHANGE_SPSR} |
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211 | |
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212 | /* Return from interrupt */ |
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213 | subs pc, lr, #4 |
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214 | |
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215 | #endif /* ARM_MULTILIB_ARCH_V4 */ |
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