1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup ScoreCPU |
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5 | * |
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6 | * @brief ARM interrupt exception prologue and epilogue. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009 |
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11 | * embedded brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * <rtems@embedded-brains.de> |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.com/license/LICENSE. |
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20 | */ |
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21 | |
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22 | /* |
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23 | * The upper EXCHANGE_SIZE bytes of the INT stack area are used for data |
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24 | * exchange between INT and SVC mode. Below of this is the actual INT stack. |
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25 | * The exchange area is only accessed if INT is disabled. |
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26 | */ |
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27 | |
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28 | #ifdef HAVE_CONFIG_H |
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29 | #include "config.h" |
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30 | #endif |
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31 | |
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32 | #include <rtems/asm.h> |
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33 | #include <rtems/score/percpu.h> |
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34 | |
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35 | #ifdef ARM_MULTILIB_ARCH_V4 |
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36 | |
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37 | #define EXCHANGE_LR r4 |
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38 | #define EXCHANGE_SPSR r5 |
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39 | #define EXCHANGE_CPSR r6 |
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40 | #define EXCHANGE_INT_SP r7 |
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41 | |
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42 | #define EXCHANGE_LIST {EXCHANGE_LR, EXCHANGE_SPSR, EXCHANGE_CPSR, EXCHANGE_INT_SP} |
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43 | #define EXCHANGE_SIZE 16 |
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44 | |
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45 | #define CONTEXT_LIST {r0, r1, r2, r3, EXCHANGE_LR, EXCHANGE_SPSR, r12} |
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46 | #define CONTEXT_SIZE 28 |
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47 | |
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48 | .extern _Thread_Dispatch_disable_level |
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49 | |
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50 | .extern bsp_interrupt_dispatch |
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51 | |
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52 | .arm |
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53 | .globl arm_exc_interrupt |
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54 | arm_exc_interrupt: |
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55 | |
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56 | /* Save exchange registers to exchange area */ |
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57 | stmdb sp, EXCHANGE_LIST |
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58 | |
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59 | /* Set exchange registers */ |
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60 | mov EXCHANGE_LR, lr |
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61 | mrs EXCHANGE_SPSR, spsr |
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62 | mrs EXCHANGE_CPSR, cpsr |
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63 | sub EXCHANGE_INT_SP, sp, #EXCHANGE_SIZE |
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64 | |
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65 | /* Switch to SVC mode */ |
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66 | orr EXCHANGE_CPSR, EXCHANGE_CPSR, #0x1 |
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67 | msr cpsr, EXCHANGE_CPSR |
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68 | |
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69 | /* |
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70 | * Save context. We save the LR separately because it has to be |
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71 | * restored in SVC mode. The other registers can be restored in INT |
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72 | * mode. |
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73 | */ |
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74 | stmdb sp!, CONTEXT_LIST |
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75 | stmdb sp!, {lr} |
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76 | |
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77 | /* Remember INT stack pointer */ |
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78 | mov r1, EXCHANGE_INT_SP |
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79 | |
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80 | /* Restore exchange registers from exchange area */ |
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81 | ldmia r1, EXCHANGE_LIST |
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82 | |
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83 | /* Get interrupt nest level */ |
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84 | ldr r0, =ISR_NEST_LEVEL |
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85 | ldr r2, [r0] |
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86 | |
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87 | /* Switch stack if necessary and save original stack pointer */ |
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88 | mov r3, sp |
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89 | cmp r2, #0 |
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90 | moveq sp, r1 |
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91 | stmdb sp!, {r3} |
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92 | |
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93 | /* Switch to THUMB instructions if necessary */ |
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94 | SWITCH_FROM_ARM_TO_THUMB r1 |
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95 | |
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96 | /* Increment interrupt nest and thread dispatch disable level */ |
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97 | ldr r1, =_Thread_Dispatch_disable_level |
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98 | ldr r3, [r1] |
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99 | add r2, #1 |
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100 | add r3, #1 |
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101 | str r2, [r0] |
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102 | str r3, [r1] |
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103 | |
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104 | /* Call BSP dependent interrupt dispatcher */ |
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105 | bl bsp_interrupt_dispatch |
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106 | |
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107 | /* Decrement interrupt nest and thread dispatch disable level */ |
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108 | ldr r0, =ISR_NEST_LEVEL |
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109 | ldr r1, =_Thread_Dispatch_disable_level |
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110 | ldr r2, [r0] |
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111 | ldr r3, [r1] |
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112 | sub r2, #1 |
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113 | sub r3, #1 |
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114 | str r2, [r0] |
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115 | str r3, [r1] |
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116 | |
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117 | /* Restore stack pointer */ |
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118 | SWITCH_FROM_THUMB_TO_ARM |
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119 | ldr sp, [sp] |
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120 | SWITCH_FROM_ARM_TO_THUMB r0 |
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121 | |
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122 | /* Check thread dispatch disable level */ |
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123 | cmp r3, #0 |
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124 | bne thread_dispatch_done |
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125 | |
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126 | /* Check context switch necessary */ |
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127 | ldr r0, =DISPATCH_NEEDED |
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128 | ldrb r1, [r0] |
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129 | cmp r1, #0 |
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130 | beq thread_dispatch_done |
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131 | |
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132 | /* This aligns thread_dispatch_done on a 4 byte boundary */ |
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133 | #ifdef __thumb__ |
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134 | nop |
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135 | #endif /* __thumb__ */ |
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136 | |
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137 | do_thread_dispatch: |
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138 | |
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139 | /* Thread dispatch */ |
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140 | bl _Thread_Dispatch |
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141 | |
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142 | thread_dispatch_done: |
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143 | |
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144 | /* Switch to ARM instructions if necessary */ |
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145 | SWITCH_FROM_THUMB_TO_ARM |
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146 | |
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147 | /* Restore link register */ |
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148 | ldmia sp!, {lr} |
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149 | |
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150 | /* |
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151 | * XXX: Remember and restore stack pointer. The data on the stack is |
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152 | * still in use. So the stack is now in an inconsistent state. The |
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153 | * FIQ handler implementation must not use this area. |
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154 | */ |
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155 | mov r0, sp |
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156 | add sp, #CONTEXT_SIZE |
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157 | |
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158 | /* Get INT mode program status register */ |
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159 | mrs r1, cpsr |
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160 | bic r1, r1, #0x1 |
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161 | |
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162 | /* Switch to INT mode */ |
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163 | msr cpsr, r1 |
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164 | |
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165 | /* Save EXCHANGE_LR and EXCHANGE_SPSR registers to exchange area */ |
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166 | stmdb sp!, {EXCHANGE_LR, EXCHANGE_SPSR} |
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167 | |
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168 | /* Restore context */ |
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169 | ldmia r0, CONTEXT_LIST |
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170 | |
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171 | /* Set return address and program status */ |
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172 | mov lr, EXCHANGE_LR |
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173 | msr spsr, EXCHANGE_SPSR |
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174 | |
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175 | /* Restore EXCHANGE_LR and EXCHANGE_SPSR registers from exchange area */ |
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176 | ldmia sp!, {EXCHANGE_LR, EXCHANGE_SPSR} |
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177 | |
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178 | /* Return from interrupt */ |
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179 | subs pc, lr, #4 |
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180 | |
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181 | #endif /* ARM_MULTILIB_ARCH_V4 */ |
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