1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup RTEMSScoreCPUARM |
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5 | * |
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6 | * @brief ARM interrupt exception prologue and epilogue. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009, 2022 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | /* |
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24 | * The upper EXCHANGE_SIZE bytes of the INT stack area are used for data |
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25 | * exchange between INT and SVC mode. Below of this is the actual INT stack. |
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26 | * The exchange area is only accessed if INT is disabled. |
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27 | */ |
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28 | |
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29 | #ifdef HAVE_CONFIG_H |
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30 | #include "config.h" |
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31 | #endif |
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32 | |
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33 | #include <rtems/asm.h> |
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34 | |
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35 | #ifdef ARM_MULTILIB_ARCH_V4 |
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36 | |
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37 | #define STACK_POINTER_ADJUST r7 |
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38 | #define NON_VOLATILE_SCRATCH r9 |
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39 | |
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40 | #define EXCHANGE_LR r4 |
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41 | #define EXCHANGE_SPSR r5 |
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42 | #define EXCHANGE_CPSR r6 |
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43 | #define EXCHANGE_INT_SP r8 |
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44 | |
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45 | #define EXCHANGE_LIST {EXCHANGE_LR, EXCHANGE_SPSR, EXCHANGE_CPSR, EXCHANGE_INT_SP} |
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46 | #define EXCHANGE_SIZE 16 |
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47 | |
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48 | #define CONTEXT_LIST {r0, r1, r2, r3, EXCHANGE_LR, EXCHANGE_SPSR, NON_VOLATILE_SCRATCH, r12} |
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49 | #define CONTEXT_SIZE 32 |
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50 | |
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51 | .arm |
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52 | .globl _ARMV4_Exception_interrupt |
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53 | _ARMV4_Exception_interrupt: |
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54 | |
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55 | /* Save exchange registers to exchange area */ |
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56 | stmdb sp, EXCHANGE_LIST |
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57 | |
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58 | /* Set exchange registers */ |
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59 | mov EXCHANGE_LR, lr |
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60 | mrs EXCHANGE_SPSR, SPSR |
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61 | mrs EXCHANGE_CPSR, CPSR |
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62 | sub EXCHANGE_INT_SP, sp, #EXCHANGE_SIZE |
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63 | |
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64 | /* Switch to SVC mode */ |
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65 | orr EXCHANGE_CPSR, EXCHANGE_CPSR, #0x1 |
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66 | msr CPSR_c, EXCHANGE_CPSR |
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67 | |
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68 | /* |
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69 | * Save context. We save the link register separately because it has |
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70 | * to be restored in SVC mode. The other registers can be restored in |
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71 | * INT mode. Ensure that the size of the saved registers is an |
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72 | * integral multiple of 8 bytes. Provide a non-volatile scratch |
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73 | * register which may be used accross function calls. |
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74 | */ |
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75 | push CONTEXT_LIST |
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76 | push {STACK_POINTER_ADJUST, lr} |
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77 | |
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78 | /* |
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79 | * On a public interface, the stack pointer must be aligned on an |
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80 | * 8-byte boundary. However, it may temporarily be only aligned on a |
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81 | * 4-byte boundary. Make sure the stack pointer is aligned on an |
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82 | * 8-byte boundary. |
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83 | */ |
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84 | and STACK_POINTER_ADJUST, sp, #0x4 |
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85 | sub sp, sp, STACK_POINTER_ADJUST |
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86 | |
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87 | /* Get per-CPU control of current processor */ |
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88 | GET_SELF_CPU_CONTROL r0 |
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89 | |
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90 | #ifdef ARM_MULTILIB_VFP |
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91 | /* Save VFP context */ |
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92 | vmrs r2, FPSCR |
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93 | vpush {d0-d7} |
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94 | #ifdef ARM_MULTILIB_VFP_D32 |
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95 | vpush {d16-d31} |
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96 | #endif |
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97 | push {r2, r3} |
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98 | #endif /* ARM_MULTILIB_VFP */ |
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99 | |
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100 | /* Remember INT stack pointer */ |
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101 | mov r1, EXCHANGE_INT_SP |
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102 | |
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103 | /* Restore exchange registers from exchange area */ |
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104 | ldmia r1, EXCHANGE_LIST |
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105 | |
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106 | /* Get interrupt nest level */ |
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107 | ldr r2, [r0, #PER_CPU_ISR_NEST_LEVEL] |
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108 | |
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109 | /* Switch stack if necessary and save original stack pointer */ |
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110 | mov NON_VOLATILE_SCRATCH, sp |
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111 | cmp r2, #0 |
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112 | moveq sp, r1 |
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113 | |
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114 | /* Increment interrupt nest and thread dispatch disable level */ |
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115 | ldr r3, [r0, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL] |
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116 | add r2, r2, #1 |
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117 | add r3, r3, #1 |
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118 | str r2, [r0, #PER_CPU_ISR_NEST_LEVEL] |
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119 | str r3, [r0, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL] |
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120 | |
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121 | /* Call BSP dependent interrupt dispatcher */ |
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122 | #ifdef RTEMS_PROFILING |
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123 | cmp r2, #1 |
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124 | bne .Lskip_profiling |
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125 | BLX_TO_THUMB_1 _CPU_Counter_read |
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126 | push {r0, r1} |
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127 | GET_SELF_CPU_CONTROL r0 |
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128 | BLX_TO_THUMB_1 bsp_interrupt_dispatch |
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129 | BLX_TO_THUMB_1 _CPU_Counter_read |
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130 | pop {r1, r3} |
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131 | mov r2, r0 |
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132 | GET_SELF_CPU_CONTROL r0 |
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133 | BLX_TO_THUMB_1 _Profiling_Outer_most_interrupt_entry_and_exit |
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134 | .Lprofiling_done: |
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135 | #else |
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136 | BLX_TO_THUMB_1 bsp_interrupt_dispatch |
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137 | #endif |
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138 | |
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139 | /* Get per-CPU control of current processor */ |
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140 | GET_SELF_CPU_CONTROL r0 |
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141 | |
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142 | /* Load some per-CPU variables */ |
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143 | ldr r12, [r0, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL] |
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144 | ldrb r1, [r0, #PER_CPU_DISPATCH_NEEDED] |
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145 | ldr r2, [r0, #PER_CPU_ISR_DISPATCH_DISABLE] |
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146 | ldr r3, [r0, #PER_CPU_ISR_NEST_LEVEL] |
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147 | |
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148 | /* Restore stack pointer */ |
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149 | mov sp, NON_VOLATILE_SCRATCH |
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150 | |
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151 | /* Decrement levels and determine thread dispatch state */ |
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152 | eor r1, r1, r12 |
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153 | sub r12, r12, #1 |
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154 | orr r1, r1, r12 |
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155 | orr r1, r1, r2 |
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156 | sub r3, r3, #1 |
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157 | |
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158 | /* Store thread dispatch disable and ISR nest levels */ |
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159 | str r12, [r0, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL] |
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160 | str r3, [r0, #PER_CPU_ISR_NEST_LEVEL] |
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161 | |
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162 | /* |
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163 | * Check thread dispatch necessary, ISR dispatch disable and thread |
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164 | * dispatch disable level. |
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165 | */ |
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166 | cmp r1, #0 |
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167 | bne .Lthread_dispatch_done |
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168 | |
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169 | /* Save CPSR in non-volatile register */ |
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170 | mrs NON_VOLATILE_SCRATCH, CPSR |
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171 | |
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172 | /* Thread dispatch */ |
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173 | |
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174 | .Ldo_thread_dispatch: |
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175 | |
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176 | /* Set ISR dispatch disable and thread dispatch disable level to one */ |
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177 | mov r12, #1 |
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178 | str r12, [r0, #PER_CPU_ISR_DISPATCH_DISABLE] |
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179 | str r12, [r0, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL] |
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180 | |
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181 | /* Call _Thread_Do_dispatch(), this function will enable interrupts */ |
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182 | bic r1, NON_VOLATILE_SCRATCH, #0x80 |
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183 | BLX_TO_THUMB_1 _Thread_Do_dispatch |
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184 | |
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185 | /* Disable interrupts */ |
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186 | msr CPSR, NON_VOLATILE_SCRATCH |
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187 | |
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188 | /* |
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189 | * Get per-CPU control of current processor. In SMP configurations, we |
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190 | * may run on another processor after the _Thread_Do_dispatch() call. |
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191 | */ |
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192 | GET_SELF_CPU_CONTROL r0 |
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193 | |
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194 | /* Check if we have to do the thread dispatch again */ |
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195 | ldrb r12, [r0, #PER_CPU_DISPATCH_NEEDED] |
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196 | cmp r12, #0 |
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197 | bne .Ldo_thread_dispatch |
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198 | |
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199 | /* We are done with thread dispatching */ |
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200 | mov r12, #0 |
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201 | str r12, [r0, #PER_CPU_ISR_DISPATCH_DISABLE] |
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202 | |
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203 | .Lthread_dispatch_done: |
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204 | |
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205 | #ifdef ARM_MULTILIB_VFP |
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206 | /* Restore VFP context */ |
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207 | pop {r2, r3} |
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208 | #ifdef ARM_MULTILIB_VFP_D32 |
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209 | vpop {d16-d31} |
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210 | #endif |
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211 | vpop {d0-d7} |
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212 | vmsr FPSCR, r2 |
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213 | #endif /* ARM_MULTILIB_VFP */ |
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214 | |
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215 | /* Undo stack pointer adjustment */ |
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216 | add sp, sp, STACK_POINTER_ADJUST |
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217 | |
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218 | /* Restore STACK_POINTER_ADJUST register and link register */ |
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219 | pop {STACK_POINTER_ADJUST, lr} |
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220 | |
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221 | /* |
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222 | * XXX: Remember and restore stack pointer. The data on the stack is |
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223 | * still in use. So the stack is now in an inconsistent state. The |
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224 | * FIQ handler implementation must not use this area. |
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225 | */ |
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226 | mov r12, sp |
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227 | add sp, #CONTEXT_SIZE |
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228 | |
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229 | /* Get INT mode program status register */ |
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230 | mrs r1, CPSR |
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231 | bic r1, r1, #0x1 |
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232 | |
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233 | /* Switch to INT mode */ |
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234 | msr CPSR_c, r1 |
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235 | |
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236 | /* Save EXCHANGE_LR and EXCHANGE_SPSR registers to exchange area */ |
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237 | push {EXCHANGE_LR, EXCHANGE_SPSR} |
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238 | |
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239 | /* Restore context */ |
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240 | ldmia r12, CONTEXT_LIST |
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241 | |
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242 | /* Set return address and program status */ |
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243 | mov lr, EXCHANGE_LR |
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244 | msr SPSR_fsxc, EXCHANGE_SPSR |
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245 | |
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246 | /* Restore EXCHANGE_LR and EXCHANGE_SPSR registers from exchange area */ |
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247 | pop {EXCHANGE_LR, EXCHANGE_SPSR} |
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248 | |
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249 | #ifdef ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE |
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250 | /* |
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251 | * We must clear reservations here, since otherwise compare-and-swap |
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252 | * atomic operations with interrupts enabled may yield wrong results. |
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253 | * A compare-and-swap atomic operation is generated by the compiler |
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254 | * like this: |
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255 | * |
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256 | * .L1: |
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257 | * ldrex r1, [r0] |
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258 | * cmp r1, r3 |
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259 | * bne .L2 |
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260 | * strex r3, r2, [r0] |
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261 | * cmp r3, #0 |
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262 | * bne .L1 |
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263 | * .L2: |
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264 | * |
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265 | * Consider the following scenario. A thread is interrupted right |
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266 | * before the strex. The interrupt updates the value using a |
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267 | * compare-and-swap sequence. Everything is fine up to this point. |
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268 | * The interrupt performs now a compare-and-swap sequence which fails |
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269 | * with a branch to .L2. The current processor has now a reservation. |
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270 | * The interrupt returns without further strex. The thread updates the |
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271 | * value using the unrelated reservation of the interrupt. |
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272 | */ |
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273 | clrex |
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274 | #endif |
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275 | |
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276 | /* Return from interrupt */ |
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277 | subs pc, lr, #4 |
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278 | |
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279 | #ifdef RTEMS_PROFILING |
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280 | .Lskip_profiling: |
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281 | BLX_TO_THUMB_1 bsp_interrupt_dispatch |
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282 | b .Lprofiling_done |
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283 | #endif |
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284 | |
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285 | #endif /* ARM_MULTILIB_ARCH_V4 */ |
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