1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief ARM interrupt exception prologue and epilogue. |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2009 |
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9 | * embedded brains GmbH |
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10 | * Obere Lagerstr. 30 |
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11 | * D-82178 Puchheim |
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12 | * Germany |
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13 | * <rtems@embedded-brains.de> |
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14 | * |
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15 | * The license and distribution terms for this file may be |
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16 | * found in the file LICENSE in this distribution or at |
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17 | * http://www.rtems.com/license/LICENSE. |
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18 | */ |
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19 | |
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20 | /* |
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21 | * These two non-volatile registers contain the program status for INT and SVC |
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22 | * mode. It is important that they are directly accessible in THUMB |
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23 | * instruction mode. |
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24 | */ |
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25 | #define MODE_INT r4 |
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26 | #define MODE_SVC r5 |
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27 | |
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28 | /* |
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29 | * These three non-volatile registers are used to exchange information between |
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30 | * INT and SVC mode. |
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31 | */ |
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32 | #define SCRATCH_0 r6 |
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33 | #define SCRATCH_1 r7 |
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34 | #define SCRATCH_2 r8 |
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35 | |
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36 | /* List of scratch registers. They will be saved and restored in INT mode. */ |
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37 | #define SCRATCH_LIST {SCRATCH_0, SCRATCH_1, SCRATCH_2} |
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38 | |
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39 | /* |
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40 | * List of all volatile registers (r0, r1, r2, r3, r12 and lr), registers |
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41 | * containing the interrupt context (return address in SCRATCH_0 and saved |
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42 | * program status in SCRATCH_1) and non-volatile registers used for modes |
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43 | * (MODE_INT and MODE_SVC). They will be saved and restored in SVC mode. |
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44 | */ |
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45 | #define TASK_CONTEXT_LIST \ |
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46 | {r0, r1, r2, r3, MODE_INT, MODE_SVC, SCRATCH_0, SCRATCH_1, r12, lr} |
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47 | |
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48 | /* |
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49 | * List of all volatile registers (r0, r1, r2, r3, r12 and lr) and the saved |
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50 | * program status (SCRATCH_0 register). They will be saved and restored in INT |
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51 | * mode. |
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52 | */ |
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53 | #define INTERRUPT_CONTEXT_LIST \ |
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54 | {r0, r1, r2, r3, SCRATCH_0, r12, lr} |
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55 | |
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56 | .extern _ISR_Thread_dispatch |
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57 | .extern _ISR_Nest_level |
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58 | .extern _Thread_Dispatch_disable_level |
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59 | .extern bsp_interrupt_dispatch |
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60 | |
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61 | .arm |
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62 | .globl arm_exc_interrupt |
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63 | arm_exc_interrupt: |
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64 | |
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65 | /* Save scratch registers on INT stack */ |
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66 | stmdb sp!, SCRATCH_LIST |
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67 | |
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68 | /* Increment interrupt nest level */ |
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69 | ldr SCRATCH_0, =_ISR_Nest_level |
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70 | ldr SCRATCH_1, [SCRATCH_0] |
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71 | add SCRATCH_2, SCRATCH_1, #1 |
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72 | str SCRATCH_2, [SCRATCH_0] |
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73 | |
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74 | /* Branch for nested interrupts */ |
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75 | cmp SCRATCH_1, #0 |
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76 | bne nested_interrupt_context_save |
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77 | |
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78 | /* Move interrupt context and CPSR to scratch registers */ |
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79 | mov SCRATCH_0, lr |
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80 | mrs SCRATCH_1, spsr |
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81 | mrs SCRATCH_2, cpsr |
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82 | |
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83 | /* Switch to SVC mode */ |
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84 | orr SCRATCH_2, SCRATCH_2, #0x1 |
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85 | msr cpsr_c, SCRATCH_2 |
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86 | |
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87 | /* Save context on SVC stack */ |
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88 | stmdb sp!, TASK_CONTEXT_LIST |
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89 | |
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90 | /* Save SVC mode program status to non-volatile register */ |
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91 | mov MODE_SVC, SCRATCH_2 |
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92 | |
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93 | /* Save INT mode program status to non-volatile register */ |
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94 | bic MODE_INT, MODE_SVC, #0x1 |
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95 | |
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96 | /* Switch to INT mode */ |
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97 | msr cpsr_c, MODE_INT |
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98 | |
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99 | /* Restore scratch registers from INT stack */ |
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100 | ldmia sp!, SCRATCH_LIST |
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101 | |
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102 | /* |
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103 | * At this point the INT stack is in the exception entry state and |
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104 | * contains no data for us. The context is saved on the SVC stack. We |
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105 | * can easily switch modes via the registers MODE_INT and MODE_SVC |
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106 | * which are valid through subroutine calls. We can use all volatile |
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107 | * registers in both modes. Note that this comment describes the non |
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108 | * nested interrupt entry. For a nested interrupt things are |
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109 | * different, since we can save everything on the INT stack and there |
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110 | * is no need to switch modes. |
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111 | */ |
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112 | |
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113 | task_context_save_done: |
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114 | |
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115 | /* Switch to THUMB instructions if necessary */ |
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116 | #ifdef __thumb__ |
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117 | add r0, pc, #1 |
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118 | bx r0 |
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119 | .thumb |
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120 | #endif /* __thumb__ */ |
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121 | |
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122 | /* Increment thread dispatch disable level */ |
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123 | ldr r1, =_Thread_Dispatch_disable_level |
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124 | ldr r3, [r1] |
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125 | add r3, r3, #1 |
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126 | str r3, [r1] |
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127 | |
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128 | /* Call BSP dependent interrrupt dispatcher */ |
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129 | bl bsp_interrupt_dispatch |
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130 | |
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131 | /* Decrement interrupt nest and thread dispatch disable level */ |
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132 | ldr r0, =_ISR_Nest_level |
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133 | ldr r1, =_Thread_Dispatch_disable_level |
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134 | ldr r2, [r0] |
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135 | ldr r3, [r1] |
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136 | sub r2, r2, #1 |
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137 | sub r3, r3, #1 |
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138 | str r2, [r0] |
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139 | str r3, [r1] |
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140 | |
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141 | /* Switch to ARM instructions if necessary */ |
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142 | #ifdef __thumb__ |
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143 | .align 2 |
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144 | bx pc |
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145 | .arm |
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146 | #endif /* __thumb__ */ |
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147 | |
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148 | /* Branch if we have a nested interrupt */ |
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149 | cmp r2, #0 |
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150 | bne nested_interrupt_return |
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151 | |
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152 | /* Branch if thread dispatching is disabled */ |
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153 | cmp r3, #0 |
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154 | bne thread_dispatch_done |
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155 | |
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156 | /* |
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157 | * Switch to SVC mode. It is important to call the thread dispatcher |
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158 | * in SVC mode since overwise the INT stack may need to store an |
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159 | * arbitrary number of contexts and it may lead to an invalid order of |
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160 | * stack operations. |
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161 | */ |
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162 | msr cpsr_c, MODE_SVC |
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163 | |
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164 | /* Call thread dispatcher */ |
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165 | #ifdef __thumb__ |
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166 | ldr r0, =_ISR_Thread_dispatch |
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167 | mov lr, pc |
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168 | bx r0 |
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169 | .thumb |
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170 | bx pc |
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171 | nop |
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172 | .arm |
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173 | #else |
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174 | bl _ISR_Thread_dispatch |
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175 | #endif |
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176 | |
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177 | /* Switch to INT mode */ |
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178 | msr cpsr_c, MODE_INT |
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179 | |
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180 | thread_dispatch_done: |
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181 | |
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182 | /* Save scratch registers on INT stack */ |
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183 | stmdb sp!, SCRATCH_LIST |
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184 | |
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185 | /* Switch to SVC mode */ |
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186 | msr cpsr_c, MODE_SVC |
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187 | |
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188 | /* Move INT mode program status to scratch register */ |
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189 | mov SCRATCH_2, MODE_INT |
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190 | |
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191 | /* Restore context from SVC stack */ |
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192 | ldmia sp!, TASK_CONTEXT_LIST |
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193 | |
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194 | /* Switch to INT mode */ |
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195 | msr cpsr_c, SCRATCH_2 |
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196 | |
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197 | /* Restore interrupt context */ |
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198 | mov lr, SCRATCH_0 |
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199 | msr spsr, SCRATCH_1 |
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200 | |
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201 | /* Restore scratch registers from INT stack */ |
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202 | ldmia sp!, SCRATCH_LIST |
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203 | |
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204 | /* Return from interrupt */ |
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205 | subs pc, lr, #4 |
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206 | |
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207 | nested_interrupt_context_save: |
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208 | |
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209 | /* Move saved program status register to scratch register */ |
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210 | mrs SCRATCH_0, spsr |
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211 | |
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212 | /* Save context on INT stack */ |
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213 | stmdb sp!, INTERRUPT_CONTEXT_LIST |
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214 | |
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215 | b task_context_save_done |
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216 | |
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217 | nested_interrupt_return: |
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218 | |
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219 | /* Restore context from INT stack */ |
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220 | ldmia sp!, INTERRUPT_CONTEXT_LIST |
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221 | |
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222 | /* Restore saved program status register */ |
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223 | msr spsr, SCRATCH_0 |
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224 | |
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225 | /* Restore scratch registers from INT stack */ |
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226 | ldmia sp!, SCRATCH_LIST |
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227 | |
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228 | /* Return from interrupt */ |
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229 | subs pc, lr, #4 |
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