source: rtems/cpukit/score/cpu/arm/arm_exc_handler_low.S @ c5ed148

4.115
Last change on this file since c5ed148 was c5ed148, checked in by Sebastian Huber <sebastian.huber@…>, on 09/24/11 at 12:56:51

2011-09-24 Sebastian Huber <sebastian.huber@…>

  • rtems/score/armv7m.h, armv7m-context-initialize.c, armv7m-context-restore.c, armv7m-context-switch.c, armv7m-exception-handler-get.c, armv7m-exception-handler-set.c, armv7m-exception-priority-get.c, armv7m-exception-priority-set.c, armv7m-initialize.c, armv7m-isr-dispatch.c, armv7m-isr-enter-leave.c, armv7m-isr-level-get.c, armv7m-isr-level-set.c, armv7m-isr-vector-install.c, armv7m-multitasking-start-stop.c: New files.
  • Makefile.am, preinstall.am: Reflect changes above.
  • rtems/score/arm.h: Define ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M.
  • rtems/score/cpu.h, cpu_asm.S, cpu.c, arm_exc_abort.S, arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S: Define CPU_HAS_HARDWARE_INTERRUPT_STACK to FALSE. Use ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M.
  • Property mode set to 100644
File size: 4.2 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup ScoreCPU
5 *
6 * @brief ARM exception support implementation.
7 */
8
9/*
10 *  $Id$
11 *
12 *  Copyright (c) 2007 by Ray Xu, <Rayx.cn@gmail.com>
13 *          Thumb support added.
14 *
15 *  Copyright (c) 2002 by Advent Networks, Inc.
16 *          Jay Monkman <jmonkman@adventnetworks.com>
17 *
18 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
19 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
20 *
21 *  The license and distribution terms for this file may be
22 *  found in the file LICENSE in this distribution or at
23 *  http://www.rtems.com/license/LICENSE.
24 *
25 *  Moved from file 'cpukit/score/cpu/arm/cpu_asm.S'.
26 *
27 */
28
29#ifdef HAVE_CONFIG_H
30#include "config.h"
31#endif
32
33#include <rtems/asm.h>
34#include <rtems/score/cpu_asm.h>
35
36#ifdef ARM_MULTILIB_ARCH_V4
37
38        .text
39
40/* FIXME:       _Exception_Handler_Undef_Swi is untested */
41DEFINE_FUNCTION_ARM(_Exception_Handler_Undef_Swi)
42/* FIXME: This should use load and store multiple instructions */
43        sub     r13,r13,#SIZE_REGS
44        str     r4,  [r13, #REG_R4]
45        str     r5,  [r13, #REG_R5]
46        str     r6,  [r13, #REG_R6]
47        str     r7,  [r13, #REG_R7]
48        str     r8,  [r13, #REG_R8]
49        str     r9,  [r13, #REG_R9]
50        str     r10, [r13, #REG_R10]
51        str     r11, [r13, #REG_R11]
52        str     sp,  [r13, #REG_SP]
53        str     lr,  [r13, #REG_LR]
54        mrs     r0,  cpsr               /* read the status */
55        and     r0,  r0,#0x1f           /* we keep the mode as exception number */
56        str     r0,  [r13, #REG_PC]     /* we store it in a free place */
57        mov     r0,  r13                /* put frame address in r0 (C arg 1) */
58
59        ldr     r1, =SWI_Handler
60        ldr     lr, =_go_back_1
61        ldr     pc,[r1]                         /* call handler  */
62_go_back_1:
63        ldr     r4,  [r13, #REG_R4]
64        ldr     r5,  [r13, #REG_R5]
65        ldr     r6,  [r13, #REG_R6]
66        ldr     r7,  [r13, #REG_R7]
67        ldr     r8,  [r13, #REG_R8]
68        ldr     r9,  [r13, #REG_R9]
69        ldr     r10, [r13, #REG_R10]
70        ldr     r11, [r13, #REG_R11]
71        ldr     sp,  [r13, #REG_SP]
72        ldr     lr,  [r13, #REG_LR]
73        add     r13,r13,#SIZE_REGS
74        movs    pc,r14                  /* return  */
75       
76/* FIXME:       _Exception_Handler_Abort is untested */
77DEFINE_FUNCTION_ARM(_Exception_Handler_Abort)
78/* FIXME: This should use load and store multiple instructions */
79        sub     r13,r13,#SIZE_REGS
80        str     r4,  [r13, #REG_R4]
81        str     r5,  [r13, #REG_R5]
82        str     r6,  [r13, #REG_R6]
83        str     r7,  [r13, #REG_R7]
84        str     r8,  [r13, #REG_R8]
85        str     r9,  [r13, #REG_R9]
86        str     sp,  [r13, #REG_R11]
87        str     lr,  [r13, #REG_SP]
88        str     lr,  [r13, #REG_LR]
89        mrs     r0,  cpsr               /* read the status */
90        and     r0,  r0,#0x1f           /* we keep the mode as exception number */
91        str     r0,  [r13, #REG_PC]     /* we store it in a free place */
92        mov     r0,  r13                /* put frame address in ro (C arg 1) */
93       
94        ldr     r1, =_currentExcHandler
95        ldr     lr, =_go_back_2
96        ldr     pc,[r1]                         /* call handler  */
97_go_back_2:
98        ldr     r4,  [r13, #REG_R4]
99        ldr     r5,  [r13, #REG_R5]
100        ldr     r6,  [r13, #REG_R6]
101        ldr     r7,  [r13, #REG_R7]
102        ldr     r8,  [r13, #REG_R8]
103        ldr     r9,  [r13, #REG_R9]
104        ldr     r10, [r13, #REG_R10]
105        ldr     sp,  [r13, #REG_R11]
106        ldr     lr,  [r13, #REG_SP]
107        ldr     lr,  [r13, #REG_LR]
108        add     r13,r13,#SIZE_REGS
109#ifdef  __thumb__
110        subs    r11, r14,#4
111        bx      r11
112        nop
113#else
114        subs    pc,r14,#4                       /* return */
115#endif
116
117#define ABORT_REGS_OFFS 32-REG_R4
118#define ABORT_SIZE_REGS SIZE_REGS+ABORT_REGS_OFFS
119       
120DEFINE_FUNCTION_ARM(_exc_data_abort)
121        sub     sp, sp, #ABORT_SIZE_REGS        /* reserve register frame */
122        stmia   sp, {r0-r11}
123        add     sp, sp, #ABORT_REGS_OFFS        /* the Context_Control structure starts by CPSR, R4, ... */
124
125        str     ip, [sp, #REG_PC]               /* store R12 (ip) somewhere, oh hackery, hackery, hack */
126        str     lr, [sp, #REG_LR]
127
128        mov     r1, lr
129        ldr     r0, [r1, #-8]                   /* r0 = bad instruction */
130        mrs     r1, spsr                        /* r1 = spsr */
131        mov     r2, r13                         /* r2 = exception frame of Context_Control type */
132#if defined(__thumb__)
133        .code 32
134        /*arm to thumb*/
135        adr     r5, to_thumb + 1
136        bx      r5
137        .code 16
138to_thumb:       
139#endif 
140        bl      do_data_abort
141#if defined(__thumb__)
142/*back to arm*/         
143        .code 16
144thumb_to_arm:
145        .align 2
146        adr r5, arm_code
147        bx      r5
148        nop
149        .code 32
150arm_code:
151#endif
152       
153        ldr     lr, [sp, #REG_LR]
154        ldr     ip, [sp, #REG_PC]               /* restore R12 (ip) */
155
156        sub     sp, sp, #ABORT_REGS_OFFS
157        ldmia   sp, {r0-r11}
158        add     sp, sp, #ABORT_SIZE_REGS
159#ifdef  __thumb__
160        subs    r11, r14, #4                    /* return to the instruction */
161        bx      r11
162        nop
163#else
164        subs    pc, r14, #4
165#endif
166                                                /* _AFTER_ the aborted one */
167
168#endif /* ARM_MULTILIB_ARCH_V4 */
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