1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /* |
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4 | * Copyright (c) 2012-2013 embedded brains GmbH. All rights reserved. |
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5 | * |
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6 | * embedded brains GmbH |
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7 | * Obere Lagerstr. 30 |
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8 | * 82178 Puchheim |
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9 | * Germany |
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10 | * <rtems@embedded-brains.de> |
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11 | * |
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12 | * Redistribution and use in source and binary forms, with or without |
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13 | * modification, are permitted provided that the following conditions |
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14 | * are met: |
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15 | * 1. Redistributions of source code must retain the above copyright |
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16 | * notice, this list of conditions and the following disclaimer. |
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17 | * 2. Redistributions in binary form must reproduce the above copyright |
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18 | * notice, this list of conditions and the following disclaimer in the |
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19 | * documentation and/or other materials provided with the distribution. |
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20 | * |
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21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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22 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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24 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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25 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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31 | * POSSIBILITY OF SUCH DAMAGE. |
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32 | */ |
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33 | |
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34 | #ifdef HAVE_CONFIG_H |
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35 | #include "config.h" |
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36 | #endif |
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37 | |
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38 | #include <inttypes.h> |
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39 | |
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40 | #include <rtems/score/cpu.h> |
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41 | #include <rtems/bspIo.h> |
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42 | |
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43 | static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context ) |
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44 | { |
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45 | #ifdef ARM_MULTILIB_VFP_D32 |
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46 | if ( vfp_context != NULL ) { |
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47 | const uint64_t *dx = &vfp_context->register_d0; |
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48 | int i; |
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49 | |
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50 | printk( |
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51 | "FPEXC = 0x%08" PRIx32 "\nFPSCR = 0x%08" PRIx32 "\n", |
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52 | vfp_context->register_fpexc, |
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53 | vfp_context->register_fpscr |
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54 | ); |
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55 | |
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56 | for ( i = 0; i < 32; ++i ) { |
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57 | uint32_t low = (uint32_t) dx[i]; |
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58 | uint32_t high = (uint32_t) (dx[i] >> 32); |
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59 | |
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60 | printk( "D%02i = 0x%08" PRIx32 "%08" PRIx32 "\n", i, high, low ); |
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61 | } |
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62 | } |
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63 | #endif |
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64 | } |
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65 | |
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66 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ) |
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67 | { |
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68 | printk( |
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69 | "\n" |
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70 | "R0 = 0x%08" PRIx32 " R8 = 0x%08" PRIx32 "\n" |
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71 | "R1 = 0x%08" PRIx32 " R9 = 0x%08" PRIx32 "\n" |
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72 | "R2 = 0x%08" PRIx32 " R10 = 0x%08" PRIx32 "\n" |
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73 | "R3 = 0x%08" PRIx32 " R11 = 0x%08" PRIx32 "\n" |
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74 | "R4 = 0x%08" PRIx32 " R12 = 0x%08" PRIx32 "\n" |
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75 | "R5 = 0x%08" PRIx32 " SP = 0x%08" PRIx32 "\n" |
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76 | "R6 = 0x%08" PRIx32 " LR = 0x%08" PRIxPTR "\n" |
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77 | "R7 = 0x%08" PRIx32 " PC = 0x%08" PRIxPTR "\n" |
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78 | #if defined(ARM_MULTILIB_ARCH_V4) |
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79 | "CPSR = 0x%08" PRIx32 " " |
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80 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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81 | "XPSR = 0x%08" PRIx32 " " |
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82 | #endif |
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83 | "VEC = 0x%08" PRIxPTR "\n", |
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84 | frame->register_r0, |
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85 | frame->register_r8, |
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86 | frame->register_r1, |
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87 | frame->register_r9, |
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88 | frame->register_r2, |
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89 | frame->register_r10, |
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90 | frame->register_r3, |
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91 | frame->register_r11, |
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92 | frame->register_r4, |
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93 | frame->register_r12, |
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94 | frame->register_r5, |
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95 | frame->register_sp, |
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96 | frame->register_r6, |
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97 | (intptr_t) frame->register_lr, |
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98 | frame->register_r7, |
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99 | (intptr_t) frame->register_pc, |
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100 | #if defined(ARM_MULTILIB_ARCH_V4) |
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101 | frame->register_cpsr, |
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102 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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103 | frame->register_xpsr, |
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104 | #endif |
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105 | (intptr_t) frame->vector |
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106 | ); |
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107 | |
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108 | _ARM_VFP_context_print( frame->vfp_context ); |
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109 | } |
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