source: rtems/cpukit/score/cpu/arm/arm-exception-frame-print.c @ e47a3b7

Last change on this file since e47a3b7 was e47a3b7, checked in by Joel Sherrill <joel@…>, on 02/16/22 at 22:54:29

score/cpu/arm: Change license to BSD-2

Updates #3053.

  • Property mode set to 100644
File size: 3.5 KB
Line 
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * Copyright (c) 2012-2013 embedded brains GmbH.  All rights reserved.
5 *
6 *  embedded brains GmbH
7 *  Obere Lagerstr. 30
8 *  82178 Puchheim
9 *  Germany
10 *  <rtems@embedded-brains.de>
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 *    notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 *    notice, this list of conditions and the following disclaimer in the
19 *    documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifdef HAVE_CONFIG_H
35#include "config.h"
36#endif
37
38#include <inttypes.h>
39
40#include <rtems/score/cpu.h>
41#include <rtems/bspIo.h>
42
43static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context )
44{
45#ifdef ARM_MULTILIB_VFP_D32
46  if ( vfp_context != NULL ) {
47    const uint64_t *dx = &vfp_context->register_d0;
48    int i;
49
50    printk(
51      "FPEXC = 0x%08" PRIx32 "\nFPSCR = 0x%08" PRIx32 "\n",
52      vfp_context->register_fpexc,
53      vfp_context->register_fpscr
54    );
55
56    for ( i = 0; i < 32; ++i ) {
57      uint32_t low = (uint32_t) dx[i];
58      uint32_t high = (uint32_t) (dx[i] >> 32);
59
60      printk( "D%02i = 0x%08" PRIx32 "%08" PRIx32 "\n", i, high, low );
61    }
62  }
63#endif
64}
65
66void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
67{
68  printk(
69    "\n"
70    "R0   = 0x%08" PRIx32 " R8  = 0x%08" PRIx32 "\n"
71    "R1   = 0x%08" PRIx32 " R9  = 0x%08" PRIx32 "\n"
72    "R2   = 0x%08" PRIx32 " R10 = 0x%08" PRIx32 "\n"
73    "R3   = 0x%08" PRIx32 " R11 = 0x%08" PRIx32 "\n"
74    "R4   = 0x%08" PRIx32 " R12 = 0x%08" PRIx32 "\n"
75    "R5   = 0x%08" PRIx32 " SP  = 0x%08" PRIx32 "\n"
76    "R6   = 0x%08" PRIx32 " LR  = 0x%08" PRIxPTR "\n"
77    "R7   = 0x%08" PRIx32 " PC  = 0x%08" PRIxPTR "\n"
78#if defined(ARM_MULTILIB_ARCH_V4)
79    "CPSR = 0x%08" PRIx32 " "
80#elif defined(ARM_MULTILIB_ARCH_V7M)
81    "XPSR = 0x%08" PRIx32 " "
82#endif
83    "VEC = 0x%08" PRIxPTR "\n",
84    frame->register_r0,
85    frame->register_r8,
86    frame->register_r1,
87    frame->register_r9,
88    frame->register_r2,
89    frame->register_r10,
90    frame->register_r3,
91    frame->register_r11,
92    frame->register_r4,
93    frame->register_r12,
94    frame->register_r5,
95    frame->register_sp,
96    frame->register_r6,
97    (intptr_t) frame->register_lr,
98    frame->register_r7,
99    (intptr_t) frame->register_pc,
100#if defined(ARM_MULTILIB_ARCH_V4)
101    frame->register_cpsr,
102#elif defined(ARM_MULTILIB_ARCH_V7M)
103    frame->register_xpsr,
104#endif
105    (intptr_t) frame->vector
106  );
107
108  _ARM_VFP_context_print( frame->vfp_context );
109}
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