source: rtems/cpukit/score/cpu/arm/arm-exception-frame-print.c @ 2f28a03

4.115
Last change on this file since 2f28a03 was 2f28a03, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 7, 2013 at 12:42:09 PM

arm: Implement CPU_Exception_frame_print()

  • Property mode set to 100644
File size: 1.5 KB
Line 
1/*
2 * Copyright (c) 2012-2013 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Obere Lagerstr. 30
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 */
14
15#ifdef HAVE_CONFIG_H
16  #include "config.h"
17#endif
18
19#include <rtems/score/cpu.h>
20#include <rtems/bspIo.h>
21
22void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
23{
24  printk(
25    "\n"
26    "R0   = 0x%08x R8  = 0x%08x\n"
27    "R1   = 0x%08x R9  = 0x%08x\n"
28    "R2   = 0x%08x R10 = 0x%08x\n"
29    "R3   = 0x%08x R11 = 0x%08x\n"
30    "R4   = 0x%08x R12 = 0x%08x\n"
31    "R5   = 0x%08x SP  = 0x%08x\n"
32    "R6   = 0x%08x LR  = 0x%08x\n"
33    "R7   = 0x%08x PC  = 0x%08x\n"
34#if defined(ARM_MULTILIB_ARCH_V4)
35    "CPSR = 0x%08x VEC = 0x%08x\n",
36#elif defined(ARM_MULTILIB_ARCH_V7M)
37    "XPSR = 0x%08x VEC = 0x%08x\n",
38#endif
39    frame->register_r0,
40    frame->register_r1,
41    frame->register_r2,
42    frame->register_r3,
43    frame->register_r4,
44    frame->register_r5,
45    frame->register_r6,
46    frame->register_r7,
47    frame->register_r8,
48    frame->register_r9,
49    frame->register_r10,
50    frame->register_r11,
51    frame->register_r12,
52    frame->register_sp,
53    frame->register_lr,
54    frame->register_pc,
55#if defined(ARM_MULTILIB_ARCH_V4)
56    frame->register_cpsr,
57#elif defined(ARM_MULTILIB_ARCH_V7M)
58    frame->register_xpsr,
59#endif
60    frame->vector
61  );
62}
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