1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @ingroup RTEMSScoreCPU |
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7 | * |
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8 | * @brief CPU Port Implementation API |
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9 | */ |
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10 | |
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11 | /* |
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12 | * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) |
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13 | * Written by Kinsey Moore <kinsey.moore@oarcorp.com> |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions |
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17 | * are met: |
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18 | * 1. Redistributions of source code must retain the above copyright |
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19 | * notice, this list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright |
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21 | * notice, this list of conditions and the following disclaimer in the |
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22 | * documentation and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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34 | * POSSIBILITY OF SUCH DAMAGE. |
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35 | */ |
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36 | |
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37 | #ifndef _RTEMS_SCORE_CPUIMPL_H |
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38 | #define _RTEMS_SCORE_CPUIMPL_H |
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39 | |
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40 | #include <rtems/score/cpu.h> |
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41 | |
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42 | /** |
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43 | * @defgroup RTEMSScoreCPUAArch64 AArch64 |
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44 | * |
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45 | * @ingroup RTEMSScoreCPU |
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46 | * |
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47 | * @brief ARM AArch64 Architecture Support |
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48 | * |
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49 | * @{ |
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50 | */ |
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51 | |
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52 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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53 | |
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54 | #define CPU_INTERRUPT_FRAME_SIZE 0x2E0 |
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55 | |
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56 | #define CPU_THREAD_LOCAL_STORAGE_VARIANT 11 |
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57 | |
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58 | #ifndef ASM |
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59 | |
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60 | #ifdef __cplusplus |
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61 | extern "C" { |
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62 | #endif |
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63 | |
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64 | RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ); |
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65 | |
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66 | typedef struct { |
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67 | uint64_t x0; |
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68 | uint64_t register_lr_original; |
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69 | uint64_t register_lr; |
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70 | uint64_t x1; |
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71 | uint64_t x2; |
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72 | uint64_t x3; |
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73 | uint64_t x4; |
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74 | uint64_t x5; |
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75 | uint64_t x6; |
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76 | uint64_t x7; |
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77 | uint64_t x8; |
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78 | uint64_t x9; |
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79 | uint64_t x10; |
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80 | uint64_t x11; |
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81 | uint64_t x12; |
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82 | uint64_t x13; |
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83 | uint64_t x14; |
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84 | uint64_t x15; |
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85 | uint64_t x16; |
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86 | uint64_t x17; |
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87 | uint64_t x18; |
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88 | uint64_t x19; |
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89 | uint64_t x20; |
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90 | uint64_t x21; |
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91 | #ifdef AARCH64_MULTILIB_VFP |
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92 | uint128_t q0; |
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93 | uint128_t q1; |
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94 | uint128_t q2; |
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95 | uint128_t q3; |
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96 | uint128_t q4; |
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97 | uint128_t q5; |
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98 | uint128_t q6; |
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99 | uint128_t q7; |
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100 | uint128_t q8; |
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101 | uint128_t q9; |
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102 | uint128_t q10; |
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103 | uint128_t q11; |
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104 | uint128_t q12; |
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105 | uint128_t q13; |
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106 | uint128_t q14; |
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107 | uint128_t q15; |
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108 | uint128_t q16; |
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109 | uint128_t q17; |
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110 | uint128_t q18; |
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111 | uint128_t q19; |
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112 | uint128_t q20; |
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113 | uint128_t q21; |
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114 | uint128_t q22; |
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115 | uint128_t q23; |
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116 | uint128_t q24; |
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117 | uint128_t q25; |
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118 | uint128_t q26; |
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119 | uint128_t q27; |
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120 | uint128_t q28; |
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121 | uint128_t q29; |
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122 | uint128_t q30; |
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123 | uint128_t q31; |
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124 | #endif /* AARCH64_MULTILIB_VFP */ |
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125 | uint64_t register_elr; |
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126 | uint64_t register_spsr; |
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127 | uint64_t register_fpsr; |
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128 | uint64_t register_fpcr; |
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129 | } CPU_Interrupt_frame; |
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130 | |
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131 | #ifdef RTEMS_SMP |
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132 | |
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133 | static inline |
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134 | struct Per_CPU_Control *_AARCH64_Get_current_per_CPU_control( void ) |
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135 | { |
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136 | struct Per_CPU_Control *cpu_self; |
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137 | uint64_t value; |
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138 | |
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139 | __asm__ volatile ( |
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140 | "mrs %0, TPIDR_EL1" : "=&r" ( value ) : : "memory" |
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141 | ); |
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142 | |
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143 | /* Use EL1 Thread ID Register (TPIDR_EL1) */ |
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144 | cpu_self = (struct Per_CPU_Control *)(uintptr_t)value; |
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145 | |
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146 | return cpu_self; |
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147 | } |
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148 | |
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149 | #define _CPU_Get_current_per_CPU_control() \ |
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150 | _AARCH64_Get_current_per_CPU_control() |
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151 | |
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152 | #endif /* RTEMS_SMP */ |
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153 | |
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154 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
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155 | |
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156 | void _CPU_Context_validate( uintptr_t pattern ); |
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157 | |
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158 | static inline void _CPU_Instruction_illegal( void ) |
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159 | { |
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160 | __asm__ volatile ( ".inst 0x0" ); |
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161 | } |
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162 | |
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163 | static inline void _CPU_Instruction_no_operation( void ) |
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164 | { |
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165 | __asm__ volatile ( "nop" ); |
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166 | } |
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167 | |
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168 | static inline void _CPU_Use_thread_local_storage( |
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169 | const Context_Control *context |
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170 | ) |
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171 | { |
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172 | __asm__ volatile ( |
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173 | "msr TPIDR_EL0, %0" : : "r" ( context->thread_id ) : "memory" |
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174 | ); |
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175 | } |
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176 | |
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177 | #ifdef __cplusplus |
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178 | } |
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179 | #endif |
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180 | |
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181 | #endif /* ASM */ |
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182 | |
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183 | /** @} */ |
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184 | |
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185 | #endif /* _RTEMS_SCORE_CPUIMPL_H */ |
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