source: rtems/cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S @ 9165349d

Last change on this file since 9165349d was 8387c52, checked in by Kinsey Moore <kinsey.moore@…>, on 09/22/20 at 13:31:34

score: Add AArch64 port

This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
  • Property mode set to 100644
File size: 2.8 KB
Line 
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/**
4 * @file
5 *
6 * @ingroup RTEMSScoreCPUAArch64
7 *
8 * @brief Implementation of _CPU_Context_volatile_clobber
9 *
10 * This file implements _CPU_Context_volatile_clobber for use in spcontext01.
11 */
12
13/*
14 * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
15 * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 * 1. Redistributions of source code must retain the above copyright
21 *    notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 *    notice, this list of conditions and the following disclaimer in the
24 *    documentation and/or other materials provided with the distribution.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#ifdef HAVE_CONFIG_H
40#include "config.h"
41#endif
42
43#include <rtems/asm.h>
44
45        .section        .text
46
47FUNCTION_ENTRY(_CPU_Context_volatile_clobber)
48
49.macro clobber_register reg
50        sub     x0, x0, #1
51        mov     \reg, x0
52.endm
53
54#ifdef AARCH64_MULTILIB_VFP
55        mrs     x1, FPCR
56        ldr     x2, =0xf000001f
57        bic     x1, x1, x2
58        and     x2, x2, x0
59        orr     x1, x1, x2
60        msr     FPCR, x1
61
62.macro clobber_vfp_register reg
63        sub     x0, x0, #1
64        fmov    \reg, x0
65.endm
66
67        clobber_vfp_register    d0
68        clobber_vfp_register    d1
69        clobber_vfp_register    d2
70        clobber_vfp_register    d3
71        clobber_vfp_register    d4
72        clobber_vfp_register    d5
73        clobber_vfp_register    d6
74        clobber_vfp_register    d7
75        clobber_vfp_register    d16
76        clobber_vfp_register    d17
77        clobber_vfp_register    d18
78        clobber_vfp_register    d19
79        clobber_vfp_register    d20
80        clobber_vfp_register    d21
81        clobber_vfp_register    d22
82        clobber_vfp_register    d23
83        clobber_vfp_register    d24
84        clobber_vfp_register    d25
85        clobber_vfp_register    d26
86        clobber_vfp_register    d27
87        clobber_vfp_register    d28
88        clobber_vfp_register    d29
89        clobber_vfp_register    d30
90        clobber_vfp_register    d31
91#endif /* AARCH64_MULTILIB_VFP */
92
93        clobber_register        x1
94        clobber_register        x2
95        clobber_register        x3
96        clobber_register        x12
97
98        ret
99
100FUNCTION_END(_CPU_Context_volatile_clobber)
Note: See TracBrowser for help on using the repository browser.