| 1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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| 2 | |
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| 3 | /** |
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| 4 | * @file |
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| 5 | * |
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| 6 | * @ingroup RTEMSScoreCPUAArch64 |
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| 7 | * |
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| 8 | * @brief Implementation of _CPU_Context_validate |
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| 9 | * |
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| 10 | * This file implements _CPU_Context_validate for use in spcontext01. |
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| 11 | */ |
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| 12 | |
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| 13 | /* |
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| 14 | * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) |
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| 15 | * Written by Kinsey Moore <kinsey.moore@oarcorp.com> |
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| 16 | * |
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| 17 | * Redistribution and use in source and binary forms, with or without |
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| 18 | * modification, are permitted provided that the following conditions |
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| 19 | * are met: |
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| 20 | * 1. Redistributions of source code must retain the above copyright |
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| 21 | * notice, this list of conditions and the following disclaimer. |
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| 22 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 23 | * notice, this list of conditions and the following disclaimer in the |
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| 24 | * documentation and/or other materials provided with the distribution. |
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| 25 | * |
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| 26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 27 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 28 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 29 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 30 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 31 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 32 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 33 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 34 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 35 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 36 | * POSSIBILITY OF SUCH DAMAGE. |
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| 37 | */ |
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| 38 | |
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| 39 | #ifdef HAVE_CONFIG_H |
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| 40 | #include "config.h" |
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| 41 | #endif |
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| 42 | |
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| 43 | #include <rtems/asm.h> |
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| 44 | #include <rtems/score/cpu.h> |
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| 45 | |
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| 46 | #define FRAME_OFFSET_X4 0x00 |
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| 47 | #define FRAME_OFFSET_X5 0x08 |
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| 48 | #define FRAME_OFFSET_X6 0x10 |
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| 49 | #define FRAME_OFFSET_X7 0x18 |
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| 50 | #define FRAME_OFFSET_X8 0x20 |
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| 51 | #define FRAME_OFFSET_X9 0x28 |
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| 52 | #define FRAME_OFFSET_X10 0x30 |
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| 53 | #define FRAME_OFFSET_X11 0x38 |
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| 54 | #define FRAME_OFFSET_LR 0x40 |
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| 55 | |
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| 56 | #ifdef AARCH64_MULTILIB_VFP |
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| 57 | #define FRAME_OFFSET_V8 0x48 |
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| 58 | #define FRAME_OFFSET_V9 0x58 |
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| 59 | #define FRAME_OFFSET_V10 0x68 |
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| 60 | #define FRAME_OFFSET_V11 0x78 |
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| 61 | #define FRAME_OFFSET_V12 0x88 |
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| 62 | #define FRAME_OFFSET_V13 0x98 |
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| 63 | #define FRAME_OFFSET_V14 0xA8 |
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| 64 | #define FRAME_OFFSET_V15 0xB8 |
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| 65 | |
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| 66 | #define FRAME_SIZE (FRAME_OFFSET_V15 + 0x10) |
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| 67 | #else |
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| 68 | #define FRAME_SIZE (FRAME_OFFSET_LR + 0x08) |
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| 69 | #endif |
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| 70 | |
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| 71 | .section .text |
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| 72 | |
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| 73 | FUNCTION_ENTRY(_CPU_Context_validate) |
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| 74 | |
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| 75 | /* Save */ |
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| 76 | |
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| 77 | sub sp, sp, #FRAME_SIZE |
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| 78 | |
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| 79 | str x4, [sp, #FRAME_OFFSET_X4] |
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| 80 | str x5, [sp, #FRAME_OFFSET_X5] |
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| 81 | str x6, [sp, #FRAME_OFFSET_X6] |
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| 82 | str x7, [sp, #FRAME_OFFSET_X7] |
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| 83 | str x8, [sp, #FRAME_OFFSET_X8] |
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| 84 | str x9, [sp, #FRAME_OFFSET_X9] |
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| 85 | str x10, [sp, #FRAME_OFFSET_X10] |
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| 86 | str x11, [sp, #FRAME_OFFSET_X11] |
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| 87 | str lr, [sp, #FRAME_OFFSET_LR] |
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| 88 | |
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| 89 | #ifdef AARCH64_MULTILIB_VFP |
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| 90 | str d8, [sp, #FRAME_OFFSET_V8] |
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| 91 | str d9, [sp, #FRAME_OFFSET_V9] |
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| 92 | str d10, [sp, #FRAME_OFFSET_V10] |
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| 93 | str d11, [sp, #FRAME_OFFSET_V11] |
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| 94 | str d12, [sp, #FRAME_OFFSET_V12] |
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| 95 | str d13, [sp, #FRAME_OFFSET_V13] |
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| 96 | str d14, [sp, #FRAME_OFFSET_V14] |
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| 97 | str d15, [sp, #FRAME_OFFSET_V15] |
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| 98 | #endif |
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| 99 | |
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| 100 | /* Fill */ |
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| 101 | |
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| 102 | /* R1 is used for temporary values */ |
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| 103 | mov x1, x0 |
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| 104 | |
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| 105 | /* R2 contains the stack pointer */ |
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| 106 | mov x2, sp |
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| 107 | |
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| 108 | .macro fill_register reg |
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| 109 | add x1, x1, #1 |
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| 110 | mov \reg, x1 |
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| 111 | .endm |
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| 112 | |
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| 113 | |
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| 114 | #ifdef AARCH64_MULTILIB_VFP |
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| 115 | /* X3 contains the FPSCR */ |
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| 116 | mrs x3, FPSR |
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| 117 | ldr x4, =0xf000001f |
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| 118 | bic x3, x3, x4 |
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| 119 | and x4, x4, x0 |
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| 120 | orr x3, x3, x4 |
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| 121 | msr FPSR, x3 |
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| 122 | #else |
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| 123 | fill_register x3 |
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| 124 | #endif |
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| 125 | |
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| 126 | fill_register x4 |
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| 127 | fill_register x5 |
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| 128 | fill_register x6 |
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| 129 | fill_register x7 |
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| 130 | fill_register x8 |
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| 131 | fill_register x9 |
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| 132 | fill_register x10 |
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| 133 | fill_register x11 |
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| 134 | fill_register x12 |
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| 135 | fill_register lr |
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| 136 | |
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| 137 | #ifdef AARCH64_MULTILIB_VFP |
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| 138 | .macro fill_vfp_register regnum |
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| 139 | add x1, x1, #1 |
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| 140 | fmov d\regnum\(), x1 |
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| 141 | fmov v\regnum\().D[1], x1 |
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| 142 | .endm |
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| 143 | |
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| 144 | fill_vfp_register 0 |
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| 145 | fill_vfp_register 1 |
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| 146 | fill_vfp_register 2 |
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| 147 | fill_vfp_register 3 |
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| 148 | fill_vfp_register 4 |
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| 149 | fill_vfp_register 5 |
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| 150 | fill_vfp_register 6 |
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| 151 | fill_vfp_register 7 |
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| 152 | fill_vfp_register 8 |
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| 153 | fill_vfp_register 9 |
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| 154 | fill_vfp_register 10 |
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| 155 | fill_vfp_register 11 |
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| 156 | fill_vfp_register 12 |
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| 157 | fill_vfp_register 13 |
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| 158 | fill_vfp_register 14 |
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| 159 | fill_vfp_register 15 |
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| 160 | fill_vfp_register 16 |
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| 161 | fill_vfp_register 17 |
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| 162 | fill_vfp_register 18 |
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| 163 | fill_vfp_register 19 |
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| 164 | fill_vfp_register 20 |
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| 165 | fill_vfp_register 21 |
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| 166 | fill_vfp_register 22 |
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| 167 | fill_vfp_register 23 |
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| 168 | fill_vfp_register 24 |
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| 169 | fill_vfp_register 25 |
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| 170 | fill_vfp_register 26 |
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| 171 | fill_vfp_register 27 |
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| 172 | fill_vfp_register 28 |
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| 173 | fill_vfp_register 29 |
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| 174 | fill_vfp_register 30 |
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| 175 | fill_vfp_register 31 |
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| 176 | #endif /* AARCH64_MULTILIB_VFP */ |
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| 177 | |
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| 178 | /* Check */ |
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| 179 | check: |
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| 180 | |
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| 181 | .macro check_register reg |
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| 182 | add x1, x1, #1 |
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| 183 | cmp \reg, x1 |
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| 184 | bne restore |
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| 185 | .endm |
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| 186 | |
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| 187 | /* A compare involving the stack pointer is deprecated */ |
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| 188 | mov x1, sp |
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| 189 | cmp x2, x1 |
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| 190 | bne restore |
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| 191 | |
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| 192 | mov x1, x0 |
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| 193 | |
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| 194 | #ifndef AARCH64_MULTILIB_VFP |
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| 195 | check_register x3 |
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| 196 | #endif |
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| 197 | |
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| 198 | check_register x4 |
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| 199 | check_register x5 |
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| 200 | check_register x6 |
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| 201 | check_register x7 |
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| 202 | check_register x8 |
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| 203 | check_register x9 |
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| 204 | check_register x10 |
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| 205 | check_register x11 |
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| 206 | check_register x12 |
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| 207 | check_register lr |
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| 208 | |
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| 209 | #ifdef AARCH64_MULTILIB_VFP |
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| 210 | b check_vfp |
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| 211 | #endif |
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| 212 | |
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| 213 | b check |
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| 214 | |
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| 215 | /* Restore */ |
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| 216 | restore: |
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| 217 | |
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| 218 | ldr x4, [sp, #FRAME_OFFSET_X4] |
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| 219 | ldr x5, [sp, #FRAME_OFFSET_X5] |
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| 220 | ldr x6, [sp, #FRAME_OFFSET_X6] |
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| 221 | ldr x7, [sp, #FRAME_OFFSET_X7] |
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| 222 | ldr x8, [sp, #FRAME_OFFSET_X8] |
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| 223 | ldr x9, [sp, #FRAME_OFFSET_X9] |
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| 224 | ldr x10, [sp, #FRAME_OFFSET_X10] |
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| 225 | ldr x11, [sp, #FRAME_OFFSET_X11] |
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| 226 | ldr lr, [sp, #FRAME_OFFSET_LR] |
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| 227 | |
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| 228 | #ifdef AARCH64_MULTILIB_VFP |
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| 229 | ldr d8, [sp, #FRAME_OFFSET_V8] |
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| 230 | ldr d9, [sp, #FRAME_OFFSET_V9] |
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| 231 | ldr d10, [sp, #FRAME_OFFSET_V10] |
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| 232 | ldr d11, [sp, #FRAME_OFFSET_V11] |
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| 233 | ldr d12, [sp, #FRAME_OFFSET_V12] |
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| 234 | ldr d13, [sp, #FRAME_OFFSET_V13] |
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| 235 | ldr d14, [sp, #FRAME_OFFSET_V14] |
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| 236 | ldr d15, [sp, #FRAME_OFFSET_V15] |
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| 237 | #endif |
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| 238 | |
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| 239 | add sp, sp, #FRAME_SIZE |
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| 240 | |
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| 241 | ret |
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| 242 | |
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| 243 | FUNCTION_END(_CPU_Context_validate) |
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| 244 | |
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| 245 | #ifdef AARCH64_MULTILIB_VFP |
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| 246 | check_vfp: |
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| 247 | |
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| 248 | .macro check_vfp_register regnum |
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| 249 | add x1, x1, #1 |
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| 250 | fmov x4, d\regnum |
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| 251 | fmov x5, v\regnum\().D[1] |
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| 252 | cmp x5, x4 |
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| 253 | bne 1f |
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| 254 | cmp x1, x4 |
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| 255 | bne 1f |
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| 256 | b 2f |
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| 257 | 1: |
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| 258 | b restore |
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| 259 | 2: |
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| 260 | .endm |
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| 261 | |
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| 262 | mrs x4, FPSR |
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| 263 | cmp x4, x3 |
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| 264 | bne restore |
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| 265 | |
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| 266 | check_vfp_register 0 |
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| 267 | check_vfp_register 1 |
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| 268 | check_vfp_register 2 |
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| 269 | check_vfp_register 3 |
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| 270 | check_vfp_register 4 |
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| 271 | check_vfp_register 5 |
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| 272 | check_vfp_register 6 |
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| 273 | check_vfp_register 7 |
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| 274 | check_vfp_register 8 |
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| 275 | check_vfp_register 9 |
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| 276 | check_vfp_register 10 |
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| 277 | check_vfp_register 11 |
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| 278 | check_vfp_register 12 |
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| 279 | check_vfp_register 13 |
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| 280 | check_vfp_register 14 |
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| 281 | check_vfp_register 15 |
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| 282 | check_vfp_register 16 |
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| 283 | check_vfp_register 17 |
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| 284 | check_vfp_register 18 |
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| 285 | check_vfp_register 19 |
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| 286 | check_vfp_register 20 |
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| 287 | check_vfp_register 21 |
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| 288 | check_vfp_register 22 |
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| 289 | check_vfp_register 23 |
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| 290 | check_vfp_register 24 |
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| 291 | check_vfp_register 25 |
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| 292 | check_vfp_register 26 |
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| 293 | check_vfp_register 27 |
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| 294 | check_vfp_register 28 |
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| 295 | check_vfp_register 29 |
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| 296 | check_vfp_register 30 |
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| 297 | check_vfp_register 31 |
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| 298 | |
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| 299 | /* Restore x4 and x5 */ |
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| 300 | mov x1, x0 |
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| 301 | fill_register x4 |
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| 302 | fill_register x5 |
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| 303 | |
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| 304 | b check |
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| 305 | #endif /* AARCH64_MULTILIB_VFP */ |
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