source: rtems/cpukit/score/cpu/a29k/rtems/score/cpu.h @ bbfdedd

4.104.114.84.95
Last change on this file since bbfdedd was bbfdedd, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 22, 2000 at 8:34:15 PM

2000-09-22 Joel Sherrill <joel@…>

  • amd.ah, cpu.c, cpu_asm.S, register.ah, sig.S, rtems/score/cpu.h: Updated and fixed minor things. Commented out offensive assembly and made applications link.
  • Property mode set to 100644
File size: 32.4 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the AMD 29K
4 *  processor.
5 *
6 *  Author:     Craig Lebakken <craigl@transition.com>
7 *
8 *  COPYRIGHT (c) 1996 by Transition Networks Inc.
9 *
10 *  To anyone who acknowledges that this file is provided "AS IS"
11 *  without any express or implied warranty:
12 *      permission to use, copy, modify, and distribute this file
13 *      for any purpose is hereby granted without fee, provided that
14 *      the above copyright notice and this notice appears in all
15 *      copies, and that the name of Transition Networks not be used in
16 *      advertising or publicity pertaining to distribution of the
17 *      software without specific, written prior permission.
18 *      Transition Networks makes no representations about the suitability
19 *      of this software for any purpose.
20 *
21 *  Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.c:
22 *
23 *  COPYRIGHT (c) 1989-1999.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.OARcorp.com/rtems/license.html.
29 *
30 *  $Id$
31 */
32/* @(#)cpu.h    10/21/96        1.11 */
33
34#ifndef __CPU_h
35#define __CPU_h
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
41#include <rtems/score/a29k.h>                /* pick up machine definitions */
42#ifndef ASM
43#include <rtems/score/a29ktypes.h>
44#endif
45
46extern unsigned int a29k_disable( void );
47extern void a29k_enable( unsigned int cookie );
48extern unsigned int a29k_getops( void );
49extern void a29k_getops_sup( void );
50extern void a29k_disable_sup( void );
51extern void a29k_enable_sup( void );
52extern void a29k_disable_all( void );
53extern void a29k_disable_all_sup( void );
54extern void a29k_enable_all( void );
55extern void a29k_enable_all_sup( void );
56extern void a29k_halt( void );
57extern void a29k_fatal_error( unsigned32 error );
58extern void a29k_as70( void );
59extern void a29k_super_mode( void );
60extern void a29k_context_switch_sup(void);
61extern void a29k_context_restore_sup(void);
62extern void a29k_context_save_sup(void);
63extern void a29k_sigdfl_sup(void);
64
65/* conditional compilation parameters */
66
67/*
68 *  Should the calls to _Thread_Enable_dispatch be inlined?
69 *
70 *  If TRUE, then they are inlined.
71 *  If FALSE, then a subroutine call is made.
72 *
73 *  Basically this is an example of the classic trade-off of size
74 *  versus speed.  Inlining the call (TRUE) typically increases the
75 *  size of RTEMS while speeding up the enabling of dispatching.
76 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
77 *  only be 0 or 1 unless you are in an interrupt handler and that
78 *  interrupt handler invokes the executive.]  When not inlined
79 *  something calls _Thread_Enable_dispatch which in turns calls
80 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
81 *  one subroutine call is avoided entirely.]
82 */
83
84#define CPU_INLINE_ENABLE_DISPATCH       TRUE
85
86/*
87 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
88 *  be unrolled one time?  In unrolled each iteration of the loop examines
89 *  two "nodes" on the chain being searched.  Otherwise, only one node
90 *  is examined per iteration.
91 *
92 *  If TRUE, then the loops are unrolled.
93 *  If FALSE, then the loops are not unrolled.
94 *
95 *  The primary factor in making this decision is the cost of disabling
96 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
97 *  body of the loop.  On some CPUs, the flash is more expensive than
98 *  one iteration of the loop body.  In this case, it might be desirable
99 *  to unroll the loop.  It is important to note that on some CPUs, this
100 *  code is the longest interrupt disable period in RTEMS.  So it is
101 *  necessary to strike a balance when setting this parameter.
102 */
103
104#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
105
106/*
107 *  Does RTEMS manage a dedicated interrupt stack in software?
108 *
109 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
110 *  If FALSE, nothing is done.
111 *
112 *  If the CPU supports a dedicated interrupt stack in hardware,
113 *  then it is generally the responsibility of the BSP to allocate it
114 *  and set it up.
115 *
116 *  If the CPU does not support a dedicated interrupt stack, then
117 *  the porter has two options: (1) execute interrupts on the
118 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
119 *  interrupt stack.
120 *
121 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
122 *
123 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
124 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
125 *  possible that both are FALSE for a particular CPU.  Although it
126 *  is unclear what that would imply about the interrupt processing
127 *  procedure on that CPU.
128 */
129
130#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
131
132/*
133 *  Does this CPU have hardware support for a dedicated interrupt stack?
134 *
135 *  If TRUE, then it must be installed during initialization.
136 *  If FALSE, then no installation is performed.
137 *
138 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
139 *
140 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
141 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
142 *  possible that both are FALSE for a particular CPU.  Although it
143 *  is unclear what that would imply about the interrupt processing
144 *  procedure on that CPU.
145 */
146
147#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
148
149/*
150 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
151 *
152 *  If TRUE, then the memory is allocated during initialization.
153 *  If FALSE, then the memory is allocated during initialization.
154 *
155 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
156 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
157 */
158
159#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
160
161/*
162 *  Does the RTEMS invoke the user's ISR with the vector number and
163 *  a pointer to the saved interrupt frame (1) or just the vector
164 *  number (0)?
165 */
166
167#define CPU_ISR_PASSES_FRAME_POINTER 0
168
169/*
170 *  Does the CPU have hardware floating point?
171 *
172 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
173 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
174 *
175 *  If there is a FP coprocessor such as the i387 or mc68881, then
176 *  the answer is TRUE.
177 *
178 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
179 *  It indicates whether or not this CPU model has FP support.  For
180 *  example, it would be possible to have an i386_nofp CPU model
181 *  which set this to false to indicate that you have an i386 without
182 *  an i387 and wish to leave floating point support out of RTEMS.
183 */
184
185#if ( A29K_HAS_FPU == 1 )
186#define CPU_HARDWARE_FP     TRUE
187#else
188#define CPU_HARDWARE_FP     FALSE
189#endif
190#define CPU_SOFTWARE_FP     FALSE
191
192/*
193 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
194 *
195 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
196 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
197 *
198 *  So far, the only CPU in which this option has been used is the
199 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
200 *  floating point registers to perform integer multiplies.  If
201 *  a function which you would not think utilize the FP unit DOES,
202 *  then one can not easily predict which tasks will use the FP hardware.
203 *  In this case, this option should be TRUE.
204 *
205 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
206 */
207
208#define CPU_ALL_TASKS_ARE_FP     FALSE
209
210/*
211 *  Should the IDLE task have a floating point context?
212 *
213 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
214 *  and it has a floating point context which is switched in and out.
215 *  If FALSE, then the IDLE task does not have a floating point context.
216 *
217 *  Setting this to TRUE negatively impacts the time required to preempt
218 *  the IDLE task from an interrupt because the floating point context
219 *  must be saved as part of the preemption.
220 */
221
222#define CPU_IDLE_TASK_IS_FP      FALSE
223
224/*
225 *  Should the saving of the floating point registers be deferred
226 *  until a context switch is made to another different floating point
227 *  task?
228 *
229 *  If TRUE, then the floating point context will not be stored until
230 *  necessary.  It will remain in the floating point registers and not
231 *  disturned until another floating point task is switched to.
232 *
233 *  If FALSE, then the floating point context is saved when a floating
234 *  point task is switched out and restored when the next floating point
235 *  task is restored.  The state of the floating point registers between
236 *  those two operations is not specified.
237 *
238 *  If the floating point context does NOT have to be saved as part of
239 *  interrupt dispatching, then it should be safe to set this to TRUE.
240 *
241 *  Setting this flag to TRUE results in using a different algorithm
242 *  for deciding when to save and restore the floating point context.
243 *  The deferred FP switch algorithm minimizes the number of times
244 *  the FP context is saved and restored.  The FP context is not saved
245 *  until a context switch is made to another, different FP task.
246 *  Thus in a system with only one FP task, the FP context will never
247 *  be saved or restored.
248 */
249
250#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
251
252/*
253 *  Does this port provide a CPU dependent IDLE task implementation?
254 *
255 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
256 *  must be provided and is the default IDLE thread body instead of
257 *  _Internal_threads_Idle_thread_body.
258 *
259 *  If FALSE, then use the generic IDLE thread body if the BSP does
260 *  not provide one.
261 *
262 *  This is intended to allow for supporting processors which have
263 *  a low power or idle mode.  When the IDLE thread is executed, then
264 *  the CPU can be powered down.
265 *
266 *  The order of precedence for selecting the IDLE thread body is:
267 *
268 *    1.  BSP provided
269 *    2.  CPU dependent (if provided)
270 *    3.  generic (if no BSP and no CPU dependent)
271 */
272
273#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
274
275/*
276 *  Does the stack grow up (toward higher addresses) or down
277 *  (toward lower addresses)?
278 *
279 *  If TRUE, then the grows upward.
280 *  If FALSE, then the grows toward smaller addresses.
281 */
282
283#define CPU_STACK_GROWS_UP               FALSE
284
285/*
286 *  The following is the variable attribute used to force alignment
287 *  of critical RTEMS structures.  On some processors it may make
288 *  sense to have these aligned on tighter boundaries than
289 *  the minimum requirements of the compiler in order to have as
290 *  much of the critical data area as possible in a cache line.
291 *
292 *  The placement of this macro in the declaration of the variables
293 *  is based on the syntactically requirements of the GNU C
294 *  "__attribute__" extension.  For example with GNU C, use
295 *  the following to force a structures to a 32 byte boundary.
296 *
297 *      __attribute__ ((aligned (32)))
298 *
299 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
300 *         To benefit from using this, the data must be heavily
301 *         used so it will stay in the cache and used frequently enough
302 *         in the executive to justify turning this on.
303 */
304
305#define CPU_STRUCTURE_ALIGNMENT
306
307/*
308 *  Define what is required to specify how the network to host conversion
309 *  routines are handled.
310 *
311 */
312
313/* #warning "Check these definitions!!!" */
314
315#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
316#define CPU_BIG_ENDIAN                           TRUE
317#define CPU_LITTLE_ENDIAN                        FALSE
318
319/*
320 *  The following defines the number of bits actually used in the
321 *  interrupt field of the task mode.  How those bits map to the
322 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
323 */
324
325#define CPU_MODES_INTERRUPT_MASK   0x00000001
326
327/*
328 *  Processor defined structures
329 *
330 *  Examples structures include the descriptor tables from the i386
331 *  and the processor control structure on the i960ca.
332 */
333
334/* may need to put some structures here.  */
335
336/*
337 * Contexts
338 *
339 *  Generally there are 2 types of context to save.
340 *     1. Interrupt registers to save
341 *     2. Task level registers to save
342 *
343 *  This means we have the following 3 context items:
344 *     1. task level context stuff::  Context_Control
345 *     2. floating point task stuff:: Context_Control_fp
346 *     3. special interrupt level context :: Context_Control_interrupt
347 *
348 *  On some processors, it is cost-effective to save only the callee
349 *  preserved registers during a task context switch.  This means
350 *  that the ISR code needs to save those registers which do not
351 *  persist across function calls.  It is not mandatory to make this
352 *  distinctions between the caller/callee saves registers for the
353 *  purpose of minimizing context saved during task switch and on interrupts.
354 *  If the cost of saving extra registers is minimal, simplicity is the
355 *  choice.  Save the same context on interrupt entry as for tasks in
356 *  this case.
357 *
358 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
359 *  care should be used in designing the context area.
360 *
361 *  On some CPUs with hardware floating point support, the Context_Control_fp
362 *  structure will not be used or it simply consist of an array of a
363 *  fixed number of bytes.   This is done when the floating point context
364 *  is dumped by a "FP save context" type instruction and the format
365 *  is not really defined by the CPU.  In this case, there is no need
366 *  to figure out the exact format -- only the size.  Of course, although
367 *  this is enough information for RTEMS, it is probably not enough for
368 *  a debugger such as gdb.  But that is another problem.
369 */
370
371typedef struct {
372    unsigned32 signal;
373    unsigned32 gr1;
374    unsigned32 rab;
375    unsigned32 PC0;
376    unsigned32 PC1;
377    unsigned32 PC2;
378    unsigned32 CHA;
379    unsigned32 CHD;
380    unsigned32 CHC;
381    unsigned32 ALU;
382    unsigned32 OPS;
383    unsigned32 tav;
384    unsigned32 lr1;
385    unsigned32 rfb;
386    unsigned32 msp;
387
388    unsigned32 FPStat0;
389    unsigned32 FPStat1;
390    unsigned32 FPStat2;
391    unsigned32 IPA;
392    unsigned32 IPB;
393    unsigned32 IPC;
394    unsigned32 Q;
395
396    unsigned32 gr96;
397    unsigned32 gr97;
398    unsigned32 gr98;
399    unsigned32 gr99;
400    unsigned32 gr100;
401    unsigned32 gr101;
402    unsigned32 gr102;
403    unsigned32 gr103;
404    unsigned32 gr104;
405    unsigned32 gr105;
406    unsigned32 gr106;
407    unsigned32 gr107;
408    unsigned32 gr108;
409    unsigned32 gr109;
410    unsigned32 gr110;
411    unsigned32 gr111;
412
413    unsigned32 gr112;
414    unsigned32 gr113;
415    unsigned32 gr114;
416    unsigned32 gr115;
417
418    unsigned32 gr116;
419    unsigned32 gr117;
420    unsigned32 gr118;
421    unsigned32 gr119;
422    unsigned32 gr120;
423    unsigned32 gr121;
424    unsigned32 gr122;
425    unsigned32 gr123;
426    unsigned32 gr124;
427
428    unsigned32 local_count;
429
430    unsigned32 locals[128];
431} Context_Control;
432
433typedef struct {
434    double      some_float_register;
435} Context_Control_fp;
436
437typedef struct {
438    unsigned32 special_interrupt_register;
439} CPU_Interrupt_frame;
440
441
442/*
443 *  The following table contains the information required to configure
444 *  the XXX processor specific parameters.
445 *
446 *  NOTE: The interrupt_stack_size field is required if
447 *        CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
448 *
449 *        The pretasking_hook, predriver_hook, and postdriver_hook,
450 *        and the do_zero_of_workspace fields are required on ALL CPUs.
451 */
452
453typedef struct {
454  void       (*pretasking_hook)( void );
455  void       (*predriver_hook)( void );
456  void       (*postdriver_hook)( void );
457  void       (*idle_task)( void );
458  boolean      do_zero_of_workspace;
459  unsigned32   idle_task_stack_size;
460  unsigned32   interrupt_stack_size;
461  unsigned32   extra_mpci_receive_server_stack;
462  void *     (*stack_allocate_hook)( unsigned32 );
463  void       (*stack_free_hook)( void* );
464  /* end of fields required on all CPUs */
465
466}   rtems_cpu_table;
467
468/*
469 *  Macros to access required entires in the CPU Table are in
470 *  the file rtems/system.h.
471 */
472
473/*
474 *  Macros to access AMD A29K specific additions to the CPU Table
475 */
476
477/* There are no CPU specific additions to the CPU Table for this port. */
478
479/*
480 *  This variable is optional.  It is used on CPUs on which it is difficult
481 *  to generate an "uninitialized" FP context.  It is filled in by
482 *  _CPU_Initialize and copied into the task's FP context area during
483 *  _CPU_Context_Initialize.
484 */
485
486SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
487
488/*
489 *  On some CPUs, RTEMS supports a software managed interrupt stack.
490 *  This stack is allocated by the Interrupt Manager and the switch
491 *  is performed in _ISR_Handler.  These variables contain pointers
492 *  to the lowest and highest addresses in the chunk of memory allocated
493 *  for the interrupt stack.  Since it is unknown whether the stack
494 *  grows up or down (in general), this give the CPU dependent
495 *  code the option of picking the version it wants to use.
496 *
497 *  NOTE: These two variables are required if the macro
498 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
499 */
500
501SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
502SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
503
504/*
505 *  With some compilation systems, it is difficult if not impossible to
506 *  call a high-level language routine from assembly language.  This
507 *  is especially true of commercial Ada compilers and name mangling
508 *  C++ ones.  This variable can be optionally defined by the CPU porter
509 *  and contains the address of the routine _Thread_Dispatch.  This
510 *  can make it easier to invoke that routine at the end of the interrupt
511 *  sequence (if a dispatch is necessary).
512 */
513
514SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
515
516/*
517 *  Nothing prevents the porter from declaring more CPU specific variables.
518 */
519
520/* XXX: if needed, put more variables here */
521
522/*
523 *  The size of the floating point context area.  On some CPUs this
524 *  will not be a "sizeof" because the format of the floating point
525 *  area is not defined -- only the size is.  This is usually on
526 *  CPUs with a "floating point save context" instruction.
527 */
528
529#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
530
531/*
532 *  Amount of extra stack (above minimum stack size) required by
533 *  system initialization thread.  Remember that in a multiprocessor
534 *  system the system intialization thread becomes the MP server thread.
535 */
536
537#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0
538
539/*
540 *  This defines the number of entries in the ISR_Vector_table managed
541 *  by RTEMS.
542 */
543
544#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
545#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
546
547/*
548 *  Should be large enough to run all RTEMS tests.  This insures
549 *  that a "reasonable" small application should not have any problems.
550 */
551
552#define CPU_STACK_MINIMUM_SIZE          (8192)
553
554/*
555 *  CPU's worst alignment requirement for data types on a byte boundary.  This
556 *  alignment does not take into account the requirements for the stack.
557 */
558
559#define CPU_ALIGNMENT              4
560
561/*
562 *  This number corresponds to the byte alignment requirement for the
563 *  heap handler.  This alignment requirement may be stricter than that
564 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
565 *  common for the heap to follow the same alignment requirement as
566 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
567 *  then this should be set to CPU_ALIGNMENT.
568 *
569 *  NOTE:  This does not have to be a power of 2.  It does have to
570 *         be greater or equal to than CPU_ALIGNMENT.
571 */
572
573#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
574
575/*
576 *  This number corresponds to the byte alignment requirement for memory
577 *  buffers allocated by the partition manager.  This alignment requirement
578 *  may be stricter than that for the data types alignment specified by
579 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
580 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
581 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
582 *
583 *  NOTE:  This does not have to be a power of 2.  It does have to
584 *         be greater or equal to than CPU_ALIGNMENT.
585 */
586
587#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
588
589/*
590 *  This number corresponds to the byte alignment requirement for the
591 *  stack.  This alignment requirement may be stricter than that for the
592 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
593 *  is strict enough for the stack, then this should be set to 0.
594 *
595 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
596 */
597
598#define CPU_STACK_ALIGNMENT        0
599
600/* ISR handler macros */
601
602/*
603 *  Disable all interrupts for an RTEMS critical section.  The previous
604 *  level is returned in _level.
605 */
606
607#define _CPU_ISR_Disable( _isr_cookie ) \
608    do{ _isr_cookie = a29k_disable(); }while(0)
609
610/*
611 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
612 *  This indicates the end of an RTEMS critical section.  The parameter
613 *  _level is not modified.
614 */
615
616#define _CPU_ISR_Enable( _isr_cookie )  \
617      do{ a29k_enable(_isr_cookie) ; }while(0)
618
619/*
620 *  This temporarily restores the interrupt to _level before immediately
621 *  disabling them again.  This is used to divide long RTEMS critical
622 *  sections into two or more parts.  The parameter _level is not
623 * modified.
624 */
625
626#define _CPU_ISR_Flash( _isr_cookie ) \
627  do{ \
628     _CPU_ISR_Enable( _isr_cookie ); \
629     _CPU_ISR_Disable( _isr_cookie ); \
630  }while(0)
631
632/*
633 *  Map interrupt level in task mode onto the hardware that the CPU
634 *  actually provides.  Currently, interrupt levels which do not
635 *  map onto the CPU in a generic fashion are undefined.  Someday,
636 *  it would be nice if these were "mapped" by the application
637 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
638 *  8 - 255 would be available for bsp/application specific meaning.
639 *  This could be used to manage a programmable interrupt controller
640 *  via the rtems_task_mode directive.
641 */
642
643#define _CPU_ISR_Set_level( new_level ) \
644  do{ \
645    if ( new_level ) a29k_disable_all(); \
646    else a29k_enable_all(); \
647  }while(0);
648
649/* end of ISR handler macros */
650
651/* Context handler macros */
652
653extern void _CPU_Context_save(
654  Context_Control *new_context
655);
656
657/*
658 *  Initialize the context to a state suitable for starting a
659 *  task after a context restore operation.  Generally, this
660 *  involves:
661 *
662 *     - setting a starting address
663 *     - preparing the stack
664 *     - preparing the stack and frame pointers
665 *     - setting the proper interrupt level in the context
666 *     - initializing the floating point context
667 *
668 *  This routine generally does not set any unnecessary register
669 *  in the context.  The state of the "general data" registers is
670 *  undefined at task start time.
671 *
672 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
673 *        point thread.  This is typically only used on CPUs where the
674 *        FPU may be easily disabled by software such as on the SPARC
675 *        where the PSR contains an enable FPU bit.
676 */
677
678#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
679                                 _isr, _entry_point, _is_fp ) \
680  do{ /* allocate 1/4 of stack for memory stack, 3/4 of stack for register stack */           \
681      unsigned32 _mem_stack_tmp = (unsigned32)(_stack_base) + (_size);  \
682      unsigned32 _reg_stack_tmp = (unsigned32)(_stack_base) + (((_size)*3)/4); \
683      _mem_stack_tmp &= ~(CPU_ALIGNMENT-1);                         \
684      _reg_stack_tmp &= ~(CPU_ALIGNMENT-1);                         \
685      _CPU_Context_save(_the_context);                              \
686      (_the_context)->msp = _mem_stack_tmp;           /* gr125 */   \
687      (_the_context)->lr1 =                                         \
688      (_the_context)->locals[1] =                                   \
689      (_the_context)->rfb = _reg_stack_tmp;           /* gr127 */   \
690      (_the_context)->gr1 = _reg_stack_tmp - 4 * 4;                 \
691      (_the_context)->rab = _reg_stack_tmp - 128 * 4; /* gr126 */   \
692      (_the_context)->local_count = 1-1;                            \
693      (_the_context)->PC1 = _entry_point;                           \
694      (_the_context)->PC0 = (unsigned32)((char *)_entry_point + 4); \
695      if (_isr) { (_the_context)->OPS |= (TD | DI); }               \
696      else                                                          \
697                { (_the_context)->OPS &= ~(TD | DI); }              \
698  }while(0)
699
700/*
701 *  This routine is responsible for somehow restarting the currently
702 *  executing task.  If you are lucky, then all that is necessary
703 *  is restoring the context.  Otherwise, there will need to be
704 *  a special assembly routine which does something special in this
705 *  case.  Context_Restore should work most of the time.  It will
706 *  not work if restarting self conflicts with the stack frame
707 *  assumptions of restoring a context.
708 */
709
710#define _CPU_Context_Restart_self( _the_context ) \
711   _CPU_Context_restore( (_the_context) )
712
713/*
714 *  The purpose of this macro is to allow the initial pointer into
715 *  a floating point context area (used to save the floating point
716 *  context) to be at an arbitrary place in the floating point
717 *  context area.
718 *
719 *  This is necessary because some FP units are designed to have
720 *  their context saved as a stack which grows into lower addresses.
721 *  Other FP units can be saved by simply moving registers into offsets
722 *  from the base of the context area.  Finally some FP units provide
723 *  a "dump context" instruction which could fill in from high to low
724 *  or low to high based on the whim of the CPU designers.
725 */
726
727#define _CPU_Context_Fp_start( _base, _offset ) \
728   ( (char *) (_base) + (_offset) )
729
730/*
731 *  This routine initializes the FP context area passed to it to.
732 *  There are a few standard ways in which to initialize the
733 *  floating point context.  The code included for this macro assumes
734 *  that this is a CPU in which a "initial" FP context was saved into
735 *  _CPU_Null_fp_context and it simply copies it to the destination
736 *  context passed to it.
737 *
738 *  Other models include (1) not doing anything, and (2) putting
739 *  a "null FP status word" in the correct place in the FP context.
740 */
741
742#define _CPU_Context_Initialize_fp( _destination ) \
743  do { \
744   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
745  } while(0)
746
747/* end of Context handler macros */
748
749/* Fatal Error manager macros */
750
751/*
752 *  This routine copies _error into a known place -- typically a stack
753 *  location or a register, optionally disables interrupts, and
754 *  halts/stops the CPU.
755 */
756
757#define _CPU_Fatal_halt( _error ) \
758        a29k_fatal_error(_error)
759
760/* end of Fatal Error manager macros */
761
762/* Bitfield handler macros */
763
764/*
765 *  This routine sets _output to the bit number of the first bit
766 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
767 *  This type may be either 16 or 32 bits wide although only the 16
768 *  least significant bits will be used.
769 *
770 *  There are a number of variables in using a "find first bit" type
771 *  instruction.
772 *
773 *    (1) What happens when run on a value of zero?
774 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
775 *    (3) The numbering may be zero or one based.
776 *    (4) The "find first bit" instruction may search from MSB or LSB.
777 *
778 *  RTEMS guarantees that (1) will never happen so it is not a concern.
779 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
780 *  _CPU_Priority_bits_index().  These three form a set of routines
781 *  which must logically operate together.  Bits in the _value are
782 *  set and cleared based on masks built by _CPU_Priority_mask().
783 *  The basic major and minor values calculated by _Priority_Major()
784 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
785 *  to properly range between the values returned by the "find first bit"
786 *  instruction.  This makes it possible for _Priority_Get_highest() to
787 *  calculate the major and directly index into the minor table.
788 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
789 *  is the first bit found.
790 *
791 *  This entire "find first bit" and mapping process depends heavily
792 *  on the manner in which a priority is broken into a major and minor
793 *  components with the major being the 4 MSB of a priority and minor
794 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
795 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
796 *  to the lowest priority.
797 *
798 *  If your CPU does not have a "find first bit" instruction, then
799 *  there are ways to make do without it.  Here are a handful of ways
800 *  to implement this in software:
801 *
802 *    - a series of 16 bit test instructions
803 *    - a "binary search using if's"
804 *    - _number = 0
805 *      if _value > 0x00ff
806 *        _value >>=8
807 *        _number = 8;
808 *
809 *      if _value > 0x0000f
810 *        _value >=8
811 *        _number += 4
812 *
813 *      _number += bit_set_table[ _value ]
814 *
815 *    where bit_set_table[ 16 ] has values which indicate the first
816 *      bit set
817 */
818
819#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
820#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
821
822#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
823
824#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
825  { \
826    (_output) = 0;   /* do something to prevent warnings */ \
827  }
828
829#endif
830
831/* end of Bitfield handler macros */
832
833/*
834 *  This routine builds the mask which corresponds to the bit fields
835 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
836 *  for that routine.
837 */
838
839#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
840
841#define _CPU_Priority_Mask( _bit_number ) \
842  ( 1 << (_bit_number) )
843
844#endif
845
846/*
847 *  This routine translates the bit numbers returned by
848 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
849 *  a major or minor component of a priority.  See the discussion
850 *  for that routine.
851 */
852
853#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
854
855#define _CPU_Priority_bits_index( _priority ) \
856  (_priority)
857
858#endif
859
860/* end of Priority handler macros */
861
862/* functions */
863
864/*
865 *  _CPU_Initialize
866 *
867 *  This routine performs CPU dependent initialization.
868 */
869
870void _CPU_Initialize(
871  rtems_cpu_table  *cpu_table,
872  void      (*thread_dispatch)()
873);
874
875/*
876 *  _CPU_ISR_install_raw_handler
877 *
878 *  This routine installs a "raw" interrupt handler directly into the
879 *  processor's vector table.
880 */
881 
882void _CPU_ISR_install_raw_handler(
883  unsigned32  vector,
884  proc_ptr    new_handler,
885  proc_ptr   *old_handler
886);
887
888/*
889 *  _CPU_ISR_install_vector
890 *
891 *  This routine installs an interrupt vector.
892 */
893
894void _CPU_ISR_install_vector(
895  unsigned32  vector,
896  proc_ptr    new_handler,
897  proc_ptr   *old_handler
898);
899
900/*
901 *  _CPU_Install_interrupt_stack
902 *
903 *  This routine installs the hardware interrupt stack pointer.
904 *
905 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
906 *         is TRUE.
907 */
908
909void _CPU_Install_interrupt_stack( void );
910
911/*
912 *  _CPU_Thread_Idle_body
913 *
914 *  This routine is the CPU dependent IDLE thread body.
915 *
916 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
917 *         is TRUE.
918 */
919
920void _CPU_Thread_Idle_body( void );
921
922/*
923 *  _CPU_Context_switch
924 *
925 *  This routine switches from the run context to the heir context.
926 */
927
928void _CPU_Context_switch(
929  Context_Control  *run,
930  Context_Control  *heir
931);
932
933/*
934 *  _CPU_Context_restore
935 *
936 *  This routine is generally used only to restart self in an
937 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
938 *
939 *  NOTE: May be unnecessary to reload some registers.
940 */
941
942void _CPU_Context_restore(
943  Context_Control *new_context
944);
945
946/*
947 *  _CPU_Context_save_fp
948 *
949 *  This routine saves the floating point context passed to it.
950 */
951
952void _CPU_Context_save_fp(
953  void **fp_context_ptr
954);
955
956/*
957 *  _CPU_Context_restore_fp
958 *
959 *  This routine restores the floating point context passed to it.
960 */
961
962void _CPU_Context_restore_fp(
963  void **fp_context_ptr
964);
965
966/*  The following routine swaps the endian format of an unsigned int.
967 *  It must be static because it is referenced indirectly.
968 *
969 *  This version will work on any processor, but if there is a better
970 *  way for your CPU PLEASE use it.  The most common way to do this is to:
971 *
972 *     swap least significant two bytes with 16-bit rotate
973 *     swap upper and lower 16-bits
974 *     swap most significant two bytes with 16-bit rotate
975 *
976 *  Some CPUs have special instructions which swap a 32-bit quantity in
977 *  a single instruction (e.g. i486).  It is probably best to avoid
978 *  an "endian swapping control bit" in the CPU.  One good reason is
979 *  that interrupts would probably have to be disabled to insure that
980 *  an interrupt does not try to access the same "chunk" with the wrong
981 *  endian.  Another good reason is that on some CPUs, the endian bit
982 *  endianness for ALL fetches -- both code and data -- so the code
983 *  will be fetched incorrectly.
984 */
985 
986#define CPU_swap_u32( value ) \
987  ((value&0xff) << 24) | (((value >> 8)&0xff) << 16) | \
988    (((value >> 16)&0xff) << 8) | ((value>>24)&0xff)
989
990#define CPU_swap_u16( value ) \
991  (((value&0xff) << 8) | ((value >> 8)&0xff))
992
993#ifdef __cplusplus
994}
995#endif
996
997#endif
Note: See TracBrowser for help on using the repository browser.