1 | ; /* @(#)register.ah 1.1 96/05/23 08:56:57, TEI */ |
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2 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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3 | ; naming of various registers |
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4 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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5 | ; /* $Id$ */ |
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6 | |
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7 | ;* File information and includes. |
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8 | |
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9 | .file "register.ah" |
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10 | .ident "@(#)register.ah 1.1 96/05/23 08:56:57, TEI\n" |
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11 | |
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12 | ;* Register Stack pointer and frame pointer registers. |
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13 | |
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14 | /* The assembly language is supposed to be Sierra High-C */ |
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15 | #if 0 |
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16 | .extern Rrsp, Rfp |
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17 | |
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18 | .reg regsp, %%Rrsp |
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19 | .reg fp, %%Rfp |
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20 | |
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21 | |
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22 | .extern RTrapReg |
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23 | .extern Rtrapreg |
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24 | |
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25 | .reg TrapReg, %%RTrapReg |
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26 | .reg trapreg, %%Rtrapreg |
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27 | |
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28 | |
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29 | ;* Operating system Interrupt handler registers (gr64-gr67) |
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30 | |
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31 | .extern ROSint0, ROSint1, ROSint2, ROSint3 |
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32 | |
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33 | .reg OSint0, %%ROSint0 |
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34 | .reg OSint1, %%ROSint1 |
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35 | .reg OSint2, %%ROSint2 |
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36 | .reg OSint3, %%ROSint3 |
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37 | |
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38 | .reg it0, %%ROSint0 |
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39 | .reg it1, %%ROSint1 |
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40 | .reg it2, %%ROSint2 |
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41 | .reg it3, %%ROSint3 |
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42 | |
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43 | |
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44 | |
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45 | ;* Operating system temporary (or scratch) registers (gr68-gr79) |
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46 | |
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47 | .extern ROStmp0, ROStmp1, ROStmp2, ROStmp3 |
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48 | .extern ROStmp4, ROStmp5, ROStmp6, ROStmp7 |
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49 | .extern ROStmp8, ROStmp9, ROStmp10, ROStmp11 |
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50 | |
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51 | .reg OStmp0, %%ROStmp0 |
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52 | .reg OStmp1, %%ROStmp1 |
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53 | .reg OStmp2, %%ROStmp2 |
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54 | .reg OStmp3, %%ROStmp3 |
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55 | |
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56 | .reg OStmp4, %%ROStmp4 |
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57 | .reg OStmp5, %%ROStmp5 |
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58 | .reg OStmp6, %%ROStmp6 |
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59 | .reg OStmp7, %%ROStmp7 |
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60 | |
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61 | .reg OStmp8, %%ROStmp8 |
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62 | .reg OStmp9, %%ROStmp9 |
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63 | .reg OStmp10, %%ROStmp10 |
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64 | .reg OStmp11, %%ROStmp11 |
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65 | |
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66 | |
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67 | .reg kt0, %%ROStmp0 |
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68 | .reg kt1, %%ROStmp1 |
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69 | .reg kt2, %%ROStmp2 |
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70 | .reg kt3, %%ROStmp3 |
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71 | |
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72 | .reg kt4, %%ROStmp4 |
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73 | .reg kt5, %%ROStmp5 |
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74 | .reg kt6, %%ROStmp6 |
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75 | .reg kt7, %%ROStmp7 |
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76 | |
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77 | .reg kt8, %%ROStmp8 |
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78 | .reg kt9, %%ROStmp9 |
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79 | .reg kt10, %%ROStmp10 |
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80 | .reg kt11, %%ROStmp11 |
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81 | |
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82 | |
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83 | .reg TempReg0, %%ROSint0 |
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84 | .reg TempReg1, %%ROSint1 |
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85 | .reg TempReg2, %%ROSint2 |
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86 | .reg TempReg3, %%ROSint3 |
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87 | |
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88 | .reg TempReg4, %%ROStmp0 |
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89 | .reg TempReg5, %%ROStmp1 |
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90 | .reg TempReg6, %%ROStmp2 |
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91 | .reg TempReg7, %%ROStmp3 |
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92 | |
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93 | .reg TempReg8, %%ROStmp4 |
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94 | .reg TempReg9, %%ROStmp5 |
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95 | .reg TempReg10, %%ROStmp6 |
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96 | .reg TempReg11, %%ROStmp7 |
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97 | |
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98 | .reg TempReg12, %%ROStmp8 |
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99 | .reg TempReg13, %%ROStmp9 |
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100 | .reg TempReg14, %%ROStmp10 |
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101 | .reg TempReg15, %%ROStmp11 |
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102 | |
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103 | |
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104 | ;* Assigned static registers |
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105 | |
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106 | .extern RSpillAddrReg, RFillAddrReg, RSignalAddrReg |
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107 | .extern Rpcb, Retc |
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108 | .extern RTimerExt, RTimerUtil, RLEDReg, RERRReg |
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109 | .extern Ret0, Ret1, Ret2, Ret3, Ret4, Ret5, Ret6, Ret7, Reta, Retb |
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110 | .extern Retx, Rety, Retz |
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111 | |
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112 | |
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113 | .reg SpillAddrReg, %%RSpillAddrReg |
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114 | .reg FillAddrReg, %%RFillAddrReg |
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115 | .reg SignalAddrReg, %%RSignalAddrReg |
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116 | .reg pcb, %%Rpcb |
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117 | |
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118 | .reg etx, %%Retx |
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119 | .reg ety, %%Rety |
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120 | .reg etz, %%Retz |
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121 | .reg eta, %%Reta |
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122 | |
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123 | .reg etb, %%Retb |
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124 | .reg etc, %%Retc |
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125 | .reg TimerExt, %%RTimerExt |
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126 | .reg TimerUtil, %%RTimerUtil |
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127 | |
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128 | .reg LEDReg, %%RLEDReg |
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129 | .reg ERRReg, %%RERRReg |
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130 | |
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131 | |
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132 | .reg et0, %%Ret0 |
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133 | .reg et1, %%Ret1 |
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134 | .reg et2, %%Ret2 |
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135 | .reg et3, %%Ret3 |
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136 | |
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137 | .reg et4, %%Ret4 |
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138 | .reg et5, %%Ret5 |
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139 | .reg et6, %%Ret6 |
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140 | .reg et7, %%Ret7 |
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141 | |
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142 | ; |
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143 | .equ SCB1REG_NUM, 88 |
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144 | .reg SCB1REG_PTR, %%Ret0 |
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145 | |
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146 | ; The floating point trap handlers need a few static registers |
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147 | |
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148 | .extern RFPStat0, RFPStat1, RFPStat2, RFPStat3 |
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149 | .extern Rheapptr, RHeapPtr, RArgvPtr |
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150 | |
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151 | .reg FPStat0, %%RFPStat0 |
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152 | .reg FPStat1, %%RFPStat1 |
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153 | .reg FPStat2, %%RFPStat2 |
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154 | .reg FPStat3, %%RFPStat3 |
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155 | |
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156 | .reg heapptr, %%Rheapptr |
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157 | .reg HeapPtr, %%RHeapPtr |
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158 | .reg ArgvPtr, %%RArgvPtr |
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159 | |
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160 | .extern RXLINXReg, RVMBCReg, RUARTReg, RETHERReg |
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161 | |
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162 | .reg XLINXReg, %%RXLINXReg |
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163 | .reg VMBCReg, %%RVMBCReg |
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164 | .reg UARTReg, %%RUARTReg |
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165 | .reg ETHERReg, %%RXLINXReg |
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166 | |
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167 | ;* Compiler and programmer registers. (gr96-gr127) |
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168 | |
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169 | .extern Rv0, Rv1, Rv2, Rv3, Rv4, Rv5, Rv6, Rv7, Rv8, Rv9 |
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170 | .extern Rv10, Rv11, Rv12, Rv13, Rv14, Rv15 |
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171 | |
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172 | .reg v0, %%Rv0 |
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173 | .reg v1, %%Rv1 |
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174 | .reg v2, %%Rv2 |
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175 | .reg v3, %%Rv3 |
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176 | |
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177 | .reg v4, %%Rv4 |
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178 | .reg v5, %%Rv5 |
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179 | .reg v6, %%Rv6 |
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180 | .reg v7, %%Rv7 |
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181 | |
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182 | .reg v8, %%Rv8 |
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183 | .reg v9, %%Rv9 |
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184 | .reg v10, %%Rv10 |
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185 | .reg v11, %%Rv11 |
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186 | |
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187 | .reg v12, %%Rv12 |
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188 | .reg v13, %%Rv13 |
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189 | .reg v14, %%Rv14 |
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190 | .reg v15, %%Rv15 |
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191 | |
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192 | .extern Rtv0, Rtv1, Rtv2, Rtv3, Rtv4 |
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193 | |
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194 | .reg tv0, %%Rtv0 |
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195 | .reg tv1, %%Rtv1 |
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196 | .reg tv2, %%Rtv2 |
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197 | .reg tv3, %%Rtv3 |
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198 | .reg tv4, %%Rtv4 |
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199 | |
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200 | ; **************************************************************************** |
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201 | ; For uatrap |
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202 | ; register definitions -- since this trap handler must allow for |
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203 | ; nested traps and interrupts such as TLB miss, protection violation, |
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204 | ; or Data Access Exception, and these trap handlers use the shared |
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205 | ; Temp registers, we must maintain our own that are safe over user- |
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206 | ; mode loads and stores. The following must be assigned global |
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207 | ; registers which are not used in INTR[0-3], TRAP[0-1], TLB miss, |
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208 | ; TLB protection violation, or data exception trap handlers. |
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209 | |
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210 | ; .reg cha_cpy, OStmp4 ; copy of CHA |
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211 | ; .reg chd_cpy, OStmp5 ; copy of CHD |
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212 | ; .reg chc_cpy, OStmp6 ; copy of CHC |
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213 | ; .reg LTemp0, OStmp7 ; local temp 0 |
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214 | ; .reg LTemp1, OStmp8 ; local temp 1 |
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215 | |
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216 | ; **************************************************************************** |
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217 | #endif |
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