source: rtems/cpukit/score/cpu/a29k/cpu_asm.S @ bbfdedd

4.104.114.84.95
Last change on this file since bbfdedd was bbfdedd, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 22, 2000 at 8:34:15 PM

2000-09-22 Joel Sherrill <joel@…>

  • amd.ah, cpu.c, cpu_asm.S, register.ah, sig.S, rtems/score/cpu.h: Updated and fixed minor things. Commented out offensive assembly and made applications link.
  • Property mode set to 100644
File size: 12.4 KB
Line 
1;/*  cpu_asm.c  ===> cpu_asm.S or cpu_asm.s
2; *
3; *  Author:  Craig Lebakken <craigl@transition.com>
4; *
5; *  COPYRIGHT (c) 1996 by Transition Networks Inc.
6; *
7; *  To anyone who acknowledges that this file is provided "AS IS"
8; *  without any express or implied warranty:
9; *   permission to use, copy, modify, and distribute this file
10; *   for any purpose is hereby granted without fee, provided that
11; *   the above copyright notice and this notice appears in all
12; *   copies, and that the name of Transition Networks not be used in
13; *   advertising or publicity pertaining to distribution of the
14; *   software without specific, written prior permission.
15; *   Transition Networks makes no representations about the suitability
16; *   of this software for any purpose.
17; *
18; *
19; *  This file contains the basic algorithms for all assembly code used
20; *  in an specific CPU port of RTEMS.  These algorithms must be implemented
21; *  in assembly language
22; *
23; *  NOTE:  This is supposed to be a .S or .s file NOT a C file.
24; *
25; *  COPYRIGHT (c) 1989-1999.
26; *  On-Line Applications Research Corporation (OAR).
27; *
28; *  The license and distribution terms for this file may be
29; *  found in the file LICENSE in this distribution or at
30; *  http://www.OARcorp.com/rtems/license.html.
31; *
32; *  $Id$
33; */
34
35;/*
36; *  This is supposed to be an assembly file.  This means that system.h
37; *  and cpu.h should not be included in a "real" cpu_asm file.  An
38; *  implementation in assembly should include "cpu_asm.h>
39; */
40
41;#include <cpu_asm.h>
42#include <register.ah>
43#include <amd.ah>
44#include <pswmacro.ah>
45;       .extern _bsp_exit
46;
47; push a register onto the struct
48        .macro  spush, sp, reg
49        store   0, 0, reg, sp           ; push register
50        add     sp, sp, 4               ; adjust stack pointer
51        .endm
52; push a register onto the struct
53        .macro  spushsr, sp, reg, sr
54        mfsr    reg, sr
55        store   0, 0, reg, sp           ; push register
56        add     sp, sp, 4               ; adjust stack pointer
57        .endm
58; pop a register from the struct
59        .macro  spop, reg, sp
60        load    0, 0, reg, sp
61        add     sp,sp,4
62        .endm
63; pop a special register from the struct
64        .macro  spopsr, sreg, reg, sp
65        load    0, 0, reg, sp
66        mtsr    sreg, reg
67        add     sp,sp,4
68        .endm
69;
70;/*
71; *  _CPU_Context_save_fp_context
72; *
73; *  This routine is responsible for saving the FP context
74; *  at *fp_context_ptr.  If the point to load the FP context
75; *  from is changed then the pointer is modified by this routine.
76; *
77; *  Sometimes a macro implementation of this is in cpu.h which dereferences
78; *  the ** and a similarly named routine in this file is passed something
79; *  like a (Context_Control_fp *).  The general rule on making this decision
80; *  is to avoid writing assembly language.
81; */
82
83;#if 0
84;void _CPU_Context_save_fp(
85;  void **fp_context_ptr
86;)
87;{
88;}
89;#endif
90        .global _CPU_Context_save_fp
91_CPU_Context_save_fp:
92        jmpi    lr0
93        nop
94
95;/*
96; *  _CPU_Context_restore_fp_context
97; *
98; *  This routine is responsible for restoring the FP context
99; *  at *fp_context_ptr.  If the point to load the FP context
100; *  from is changed then the pointer is modified by this routine.
101; *
102; *  Sometimes a macro implementation of this is in cpu.h which dereferences
103; *  the ** and a similarly named routine in this file is passed something
104; *  like a (Context_Control_fp *).  The general rule on making this decision
105; *  is to avoid writing assembly language.
106; */
107
108;#if 0
109;void _CPU_Context_restore_fp(
110;  void **fp_context_ptr
111;)
112;{
113;}
114;#endif
115        .global __CPU_Context_restore_fp
116__CPU_Context_restore_fp:
117        jmpi    lr0
118        nop
119
120;/*  _CPU_Context_switch
121; *
122; *  This routine performs a normal non-FP context switch.
123; */
124;#if 0
125;void _CPU_Context_switch(
126;  Context_Control  *run,
127;  Context_Control  *heir
128;)
129;{
130;}
131;#endif
132        .global __CPU_Context_switch
133__CPU_Context_switch:
134        asneq   106, gr1, gr1                           ; syscall
135        jmpi    lr0                                     ;
136        nop                                             ;
137
138
139
140        .global _a29k_context_switch_sup
141_a29k_context_switch_sup:
142#if 0
143        add     pcb,lr2,0
144        add     kt1,lr3,0       ;move heir pointer to safe location
145        constn  it0,SIG_SYNC
146        spush   pcb,it0
147        spush   pcb,gr1
148        spush   pcb,rab         ;push rab
149        spushsr pcb,it0,pc0     ;push specials
150        spushsr pcb,it0,pc1
151        add     pcb,pcb,1*4     ;space pc2
152        spushsr pcb,it0,CHA     ;push CHA
153        spushsr pcb,it0,CHD     ;push CHD
154        spushsr pcb,it0,CHC     ;push CHC
155        add     pcb,pcb,1*4     ;space for alu
156        spushsr pcb,it0,ops     ;push OPS
157        mfsr    kt0,cps         ;current status
158        const   it1,FZ          ;FZ constant
159        andn    it1,kt0,it1     ;clear FZ bit
160        mtsr    cps,it1         ;cps without FZ
161        add     pcb,pcb,1*4     ;space for tav
162        mtsrim  chc,0           ;possible DERR
163;
164        spush   pcb,lr1         ;push R-stack
165        spush   pcb,rfb         ; support
166        spush   pcb,msp         ;push M-stack pnt.
167;
168        add     pcb,pcb,3*4     ;space for floating point
169;       spush   pcb,FPStat0     ;floating point
170;       spush   pcb,FPStat1
171;       spush   pcb,FPStat2
172;
173        add     pcb,pcb,4*4     ;space for IPA..Q
174;
175        mtsrim  cr,29-1
176        storem  0,0,gr96,pcb    ;push gr96-124, optional
177        add     pcb,pcb,29*4    ;space for gr96-124
178;
179        sub     it0,rfb,gr1     ;get bytes in cache
180        srl     it0,it0,2       ;adjust to words
181        sub     it0,it0,1
182        spush   pcb,it0
183        mtsr    cr,it0
184        storem  0,0,lr0,pcb     ;save lr0-rfb
185;
186context_restore:
187        add     pcb,kt1,0       ;pcb=heir
188        add     pcb,pcb,4       ;space for signal num
189        spop    gr1,pcb         ;restore freeze registers
190        add     gr1,gr1,0       ;alu op
191        add     pcb,pcb,9*4     ;move past freeze registers
192        add     pcb,pcb,1*4     ;space for tav
193        spop    lr1,pcb
194        spop    rfb,pcb
195        spop    msp,pcb
196;       spop    FPStat0,pcb
197;       spop    FPStat1,pcb
198;       spop    FPStat2,pcb
199        add     pcb,pcb,3*4     ;space for floating point
200        add     pcb,pcb,4*4     ;space for IPA..Q
201        mtsrim  cr,29-1
202        loadm   0,0,gr96,pcb    ;pop gr96-gr124
203        add     pcb,pcb,29*4    ;space for gr96-124
204
205        spop    it1,pcb         ;pop locals count
206        mtsr    cr,it1
207        loadm   0,0,lr0,pcb     ;load locals
208       
209        add     pcb,kt1,0       ;pcb=heir
210        mtsr    cps,kt0         ;cps with FZ
211        nop
212        add     pcb,pcb,4       ;space for signal num
213        spop    gr1,pcb         ;restore freeze registers
214        add     gr1,gr1,0       ;alu op
215        spop    rab,pcb
216        spopsr  pc0,it1,pcb
217        spopsr  pc1,it1,pcb
218        add     pcb,pcb,4       ;space for pc2
219        spopsr  CHA,it1,pcb
220        spopsr  CHD,it1,pcb
221        spopsr  CHC,it1,pcb
222        add     pcb,pcb,4       ;space for alu
223        spopsr  ops,it1,pcb
224        nop
225        iret
226#endif
227
228
229;/*
230; *  _CPU_Context_restore
231; *
232; *  This routine is generally used only to restart self in an
233; *  efficient manner.  It may simply be a label in _CPU_Context_switch.
234; *
235; *  NOTE: May be unnecessary to reload some registers.
236; */
237;#if 0
238;void _CPU_Context_restore(
239;  Context_Control *new_context
240;)
241;{
242;}
243;#endif
244
245        .global __CPU_Context_restore
246__CPU_Context_restore:
247#if 0
248        asneq   107, gr1, gr1                   ; syscall
249        jmpi    lr0                                     ;
250        nop                                             ;
251
252        .global _a29k_context_restore_sup
253_a29k_context_restore_sup:
254        add     kt1,lr2,0       ;kt1 = restore context
255        mfsr    kt0,cps         ;current status
256        const   it1,FZ          ;FZ constant
257        andn    it1,kt0,it1     ;clear FZ bit
258        mtsr    cps,it1         ;cps without FZ
259        jmp     context_restore
260        nop
261
262        .global _a29k_context_save_sup
263_a29k_context_save_sup:
264        add     pcb,lr2,0
265        constn  it0,SIG_SYNC
266        spush   pcb,it0
267        spush   pcb,gr1
268        spush   pcb,rab         ;push rab
269        spushsr pcb,it0,pc0     ;push specials
270        spushsr pcb,it0,pc1
271        add     pcb,pcb,1*4     ;space pc2
272        spushsr pcb,it0,CHA     ;push CHA
273        spushsr pcb,it0,CHD     ;push CHD
274        spushsr pcb,it0,CHC     ;push CHC
275        add     pcb,pcb,1*4     ;space for alu
276        spushsr pcb,it0,ops     ;push OPS
277        mfsr    it0,cps         ;current status
278SaveFZState     it1,it2
279        add     pcb,pcb,1*4     ;space for tav
280        mtsrim  chc,0           ;possible DERR
281;
282        spush   pcb,lr1         ;push R-stack
283        spush   pcb,rfb         ; support
284        spush   pcb,msp         ;push M-stack pnt.
285;
286        spush   pcb,FPStat0     ;floating point
287        spush   pcb,FPStat1     
288        spush   pcb,FPStat2
289;
290        add     pcb,pcb,4*4     ;space for IPA..Q
291;
292        mtsrim  cr,29-1
293        storem  0,0,gr96,pcb    ;push gr96-124, optional
294        add     pcb,pcb,29*4    ;space for gr96-124
295;
296        sub     kt0,rfb,gr1     ;get bytes in cache
297        srl     kt0,kt0,2       ;adjust to words
298        sub     kt0,kt0,1       
299        spush   pcb,kt0         ;push number of words
300        mtsr    cr,kt0
301        storem  0,0,lr0,pcb     ;save lr0-rfb
302;
303        mtsr    cps,it0         ;cps with FZ
304RestoreFZState  it1,it2
305
306        nop
307        nop
308        nop
309;
310        iret
311;
312#endif
313
314        .global __CPU_Context_save
315__CPU_Context_save:
316#if 0
317        asneq   108, gr1, gr1                   ; syscall
318        jmpi    lr0                                     ;
319        nop                                             ;
320#endif
321
322
323;/*  void __ISR_Handler()
324; *
325; *  This routine provides the RTEMS interrupt management.
326; *
327; */
328
329;#if 0
330;void _ISR_Handler()
331;{
332;   /*
333;    *  This discussion ignores a lot of the ugly details in a real
334;    *  implementation such as saving enough registers/state to be
335;    *  able to do something real.  Keep in mind that the goal is
336;    *  to invoke a user's ISR handler which is written in C and
337;    *  uses a certain set of registers.
338;    *
339;    *  Also note that the exact order is to a large extent flexible.
340;    *  Hardware will dictate a sequence for a certain subset of
341;    *  _ISR_Handler while requirements for setting
342;    */
343
344;  /*
345;   *  At entry to "common" _ISR_Handler, the vector number must be
346;   *  available.  On some CPUs the hardware puts either the vector
347;   *  number or the offset into the vector table for this ISR in a
348;   *  known place.  If the hardware does not give us this information,
349;   *  then the assembly portion of RTEMS for this port will contain
350;   *  a set of distinct interrupt entry points which somehow place
351;   *  the vector number in a known place (which is safe if another
352;   *  interrupt nests this one) and branches to _ISR_Handler.
353;   *
354;   *  save some or all context on stack
355;   *  may need to save some special interrupt information for exit
356;   *
357;   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
358;   *    if ( _ISR_Nest_level == 0 )
359;   *      switch to software interrupt stack
360;   *  #endif
361;   *
362;   *  _ISR_Nest_level++;
363;   *
364;   *  _Thread_Dispatch_disable_level++;
365;   *
366;   *  (*_ISR_Vector_table[ vector ])( vector );
367;   *
368;   *  --_ISR_Nest_level;
369;   *
370;   *  if ( _ISR_Nest_level )
371;   *    goto the label "exit interrupt (simple case)"
372;   *
373;   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
374;   *    restore stack
375;   *  #endif
376;   * 
377;   *  if ( !_Context_Switch_necessary )
378;   *    goto the label "exit interrupt (simple case)"
379;   * 
380;   *  if ( !_ISR_Signals_to_thread_executing )
381;   *    goto the label "exit interrupt (simple case)"
382;   *
383;   *  call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
384;   *
385;   *  prepare to get out of interrupt
386;   *  return from interrupt  (maybe to _ISR_Dispatch)
387;   *
388;   *  LABEL "exit interrupt (simple case):
389;   *  prepare to get out of interrupt
390;   *  return from interrupt
391;   */
392;}
393;#endif
394;        .global __ISR_Handler
395;__ISR_Handler:
396;       jmpi lr0
397;        nop
398
399        .global _a29k_getops
400_a29k_getops:
401#if 0
402        asneq 113, gr96, gr96
403        jmpi lr0
404        nop
405#endif
406
407        .global _a29k_getops_sup
408_a29k_getops_sup:
409#if 0
410        mfsr    gr96, ops       ; caller wants ops
411        iret
412        nop
413#endif
414
415        .global _a29k_disable
416_a29k_disable:
417#if 0
418        asneq 110, gr96, gr96
419        jmpi lr0
420        nop
421#endif
422
423        .global _a29k_disable_sup
424_a29k_disable_sup:
425#if 0
426        mfsr    kt0, ops
427        add     gr96, kt0, 0    ; return ops to caller
428        const   kt1, (DI | TD)
429        consth  kt1, (DI | TD)
430        or      kt1, kt0, kt1
431        mtsr    ops, kt1
432        iret
433        nop
434#endif
435
436        .global _a29k_disable_all
437_a29k_disable_all:
438#if 0
439        asneq 112, gr96, gr96
440        jmpi lr0
441        nop
442#endif
443
444        .global _a29k_disable_all_sup
445_a29k_disable_all_sup:
446#if 0
447        mfsr    kt0, ops
448        const   kt1, (DI | TD)
449        consth  kt1, (DI | TD)
450        or      kt1, kt0, kt1
451        mtsr    ops, kt1
452        iret
453        nop
454#endif
455
456        .global _a29k_enable_all
457_a29k_enable_all:
458#if 0
459        asneq 111, gr96, gr96
460        jmpi lr0
461        nop
462#endif
463
464        .global _a29k_enable_all_sup
465_a29k_enable_all_sup:
466#if 0
467        mfsr    kt0, ops
468        const   kt1, (DI | TD)
469        consth  kt1, (DI | TD)
470        andn    kt1, kt0, kt1
471        mtsr    ops, kt1
472        iret
473        nop
474#endif
475
476        .global _a29k_enable
477_a29k_enable:
478#if 0
479        asneq 109, gr96, gr96
480        jmpi lr0
481        nop
482#endif
483
484        .global _a29k_enable_sup
485_a29k_enable_sup:
486#if 0
487        mfsr    kt0, ops
488        const   kt1, (DI | TD)
489        consth  kt1, (DI | TD)
490        and     kt3, lr2, kt1
491        andn    kt0, kt0, kt1
492        or      kt1, kt0, kt3
493        mtsr    ops, kt1
494        iret
495        nop
496#endif
497
498        .global _a29k_halt
499_a29k_halt:
500#if 0
501        halt
502        jmp _a29k_halt
503        nop
504#endif
505
506        .global _a29k_super_mode
507_a29k_super_mode:
508#if 0
509        mfsr gr96, ops
510        or gr96, gr96, 0x10
511        mtsr ops, gr96
512        iret
513        nop
514#endif
515
516        .global _a29k_as70
517_a29k_as70:
518#if 0
519        asneq 70,gr96,gr96
520        jmpi lr0
521        nop
522#endif
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