source: rtems/cpukit/score/cpu/a29k/cpu.c @ a4d97d94

4.104.114.84.95
Last change on this file since a4d97d94 was a4d97d94, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 18, 1996 at 8:45:27 PM

new files submitted by Craig Lebakken (lebakken@…) and Derrick Ostertag
(ostertag@…).

  • Property mode set to 100644
File size: 6.8 KB
Line 
1/*
2 *  AMD 29K CPU Dependent Source
3 *
4 *  Author:     Craig Lebakken <craigl@transition.com>
5 *
6 *  COPYRIGHT (c) 1996 by Transition Networks Inc.
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of Transition Networks not be used in
14 *      advertising or publicity pertaining to distribution of the
15 *      software without specific, written prior permission.
16 *      Transition Networks makes no representations about the suitability
17 *      of this software for any purpose.
18 *
19 *  Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
20 *
21 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
22 *  On-Line Applications Research Corporation (OAR).
23 *  All rights assigned to U.S. Government, 1994.
24 *
25 *  This material may be reproduced by or for the U.S. Government pursuant
26 *  to the copyright license under the clause at DFARS 252.227-7013.  This
27 *  notice must appear in all copies of this file and its derivatives.
28 *
29 *  $Id$
30 */
31#ifndef lint
32static char _sccsid[] = "@(#)cpu.c 21 Aug 1996     1.6\n";
33#endif
34
35#include <rtems/system.h>
36#include <rtems/score/isr.h>
37#include <rtems/score/wkspace.h>
38#include <rtems/score/thread.h>
39#include <stdio.h>
40#include <stdlib.h>
41
42void a29k_ISR_Handler(unsigned32 vector);
43
44/*  _CPU_Initialize
45 *
46 *  This routine performs processor dependent initialization.
47 *
48 *  INPUT PARAMETERS:
49 *    cpu_table       - CPU table to initialize
50 *    thread_dispatch - address of disptaching routine
51 */
52
53
54void _CPU_Initialize(
55  rtems_cpu_table  *cpu_table,
56  void      (*thread_dispatch)()      /* ignored on this CPU */
57)
58{
59  unsigned int i;
60  /*
61   *  The thread_dispatch argument is the address of the entry point
62   *  for the routine called at the end of an ISR once it has been
63   *  decided a context switch is necessary.  On some compilation
64   *  systems it is difficult to call a high-level language routine
65   *  from assembly.  This allows us to trick these systems.
66   *
67   *  If you encounter this problem save the entry point in a CPU
68   *  dependent variable.
69   */
70
71  _CPU_Thread_dispatch_pointer = thread_dispatch;
72
73  /*
74   *  If there is not an easy way to initialize the FP context
75   *  during Context_Initialize, then it is usually easier to
76   *  save an "uninitialized" FP context here and copy it to
77   *  the task's during Context_Initialize.
78   */
79
80  /* FP context initialization support goes here */
81
82  _CPU_Table = *cpu_table;
83
84  for ( i = 0; i < ISR_NUMBER_OF_VECTORS; i++ )
85  {
86     _ISR_Vector_table[i] = (proc_ptr)NULL;
87  }
88}
89
90/*PAGE
91 *
92 *  _CPU_ISR_Get_level
93 */
94 
95unsigned32 _CPU_ISR_Get_level( void )
96{
97  /*
98   *  This routine returns the current interrupt level.
99   */
100   return 0;
101}
102
103/*PAGE
104 *
105 *  _CPU_ISR_install_raw_handler
106 */
107 
108extern void intr14( void );
109extern void intr3( void );
110extern void intr2( void );
111
112void _CPU_ISR_install_raw_handler(
113  unsigned32  vector,
114  proc_ptr    new_handler,
115  proc_ptr   *old_handler
116)
117{
118  /*
119   *  This is where we install the interrupt handler into the "raw" interrupt
120   *  table used by the CPU to dispatch interrupt handlers.
121   */
122   switch( vector )
123   {
124      case 14:
125         _settrap( vector, intr14 );
126         break;
127      case 3:
128         _settrap( vector, intr3 );
129         break;
130      case 2:
131         _settrap( vector, intr2 );
132         break;
133      default:
134         break;
135   }
136}
137
138
139/*PAGE
140 *
141 *  _CPU_ISR_install_vector
142 *
143 *  This kernel routine installs the RTEMS handler for the
144 *  specified vector.
145 *
146 *  Input parameters:
147 *    vector      - interrupt vector number
148 *    old_handler - former ISR for this vector number
149 *    new_handler - replacement ISR for this vector number
150 *
151 *  Output parameters:  NONE
152 *
153 */
154
155void _CPU_ISR_install_vector(
156  unsigned32  vector,
157  proc_ptr    new_handler,
158  proc_ptr   *old_handler
159)
160{
161   *old_handler = _ISR_Vector_table[ vector ];
162
163   /*
164    *  If the interrupt vector table is a table of pointer to isr entry
165    *  points, then we need to install the appropriate RTEMS interrupt
166    *  handler for this vector number.
167    */
168
169   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
170
171   /*
172    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
173    *  be used by the _ISR_Handler so the user gets control.
174    */
175
176    _ISR_Vector_table[ vector ] = new_handler;
177}
178
179/*PAGE
180 *
181 *  _CPU_Install_interrupt_stack
182 */
183
184void _CPU_Install_interrupt_stack( void )
185{
186}
187
188/*PAGE
189 *
190 *  _CPU_Internal_threads_Idle_thread_body
191 *
192 *  NOTES:
193 *
194 *  1. This is the same as the regular CPU independent algorithm.
195 *
196 *  2. If you implement this using a "halt", "idle", or "shutdown"
197 *     instruction, then don't forget to put it in an infinite loop.
198 *
199 *  3. Be warned. Some processors with onboard DMA have been known
200 *     to stop the DMA if the CPU were put in IDLE mode.  This might
201 *     also be a problem with other on-chip peripherals.  So use this
202 *     hook with caution.
203 */
204
205void _CPU_Internal_threads_Idle_thread_body( void )
206{
207
208  for( ; ; )
209  {
210  }
211    /* insert your "halt" instruction here */ ;
212}
213
214void a29k_fatal_error( unsigned32 error )
215{
216   printf("\n\nfatal error %d, rebooting!!!\n",error );
217   exit(error);
218}
219
220   /*
221    *  This discussion ignores a lot of the ugly details in a real
222    *  implementation such as saving enough registers/state to be
223    *  able to do something real.  Keep in mind that the goal is
224    *  to invoke a user's ISR handler which is written in C and
225    *  uses a certain set of registers.
226    *
227    *  Also note that the exact order is to a large extent flexible.
228    *  Hardware will dictate a sequence for a certain subset of
229    *  _ISR_Handler while requirements for setting
230    */
231
232  /*
233   *  At entry to "common" _ISR_Handler, the vector number must be
234   *  available.  On some CPUs the hardware puts either the vector
235   *  number or the offset into the vector table for this ISR in a
236   *  known place.  If the hardware does not give us this information,
237   *  then the assembly portion of RTEMS for this port will contain
238   *  a set of distinct interrupt entry points which somehow place
239   *  the vector number in a known place (which is safe if another
240   *  interrupt nests this one) and branches to _ISR_Handler.
241   *
242   */
243
244void a29k_ISR_Handler(unsigned32 vector)
245{
246   _ISR_Nest_level++;
247   _Thread_Dispatch_disable_level++;
248   if ( _ISR_Vector_table[ vector ] )
249      (*_ISR_Vector_table[ vector ])( vector );
250   --_Thread_Dispatch_disable_level;
251   --_ISR_Nest_level;
252   if ( !_Thread_Dispatch_disable_level && !_ISR_Nest_level &&
253    (_Context_Switch_necessary || _ISR_Signals_to_thread_executing ))
254      _Thread_Dispatch();
255   return;
256}
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