source: rtems/cpukit/score/cpu/a29k/cpu.c @ 3ab90627

4.104.114.84.95
Last change on this file since 3ab90627 was 3ab90627, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 11, 2003 at 11:43:36 PM

2003-02-11 Joel Sherrill <joel@…>

  • cpu_asm.c: Rework logic that decides when to call _Thread_Dispatch. Analysis by Sergei Organov <osv@…> determined that _ISR_Signals_to_thread_executing was not being honored and/or cleared properly.
  • Property mode set to 100644
File size: 7.1 KB
Line 
1/*
2 *  AMD 29K CPU Dependent Source
3 *
4 *  Author:     Craig Lebakken <craigl@transition.com>
5 *
6 *  COPYRIGHT (c) 1996 by Transition Networks Inc.
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of Transition Networks not be used in
14 *      advertising or publicity pertaining to distribution of the
15 *      software without specific, written prior permission.
16 *      Transition Networks makes no representations about the suitability
17 *      of this software for any purpose.
18 *
19 *  Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
20 *
21 *  COPYRIGHT (c) 1989-1999.
22 *  On-Line Applications Research Corporation (OAR).
23 *
24 *  The license and distribution terms for this file may be
25 *  found in the file LICENSE in this distribution or at
26 *  http://www.OARcorp.com/rtems/license.html.
27 *
28 *  $Id$
29 */
30#ifndef lint
31static char _sccsid[] = "@(#)cpu.c 10/21/96     1.8\n";
32#endif
33
34#include <rtems/system.h>
35#include <rtems/score/isr.h>
36#include <rtems/score/wkspace.h>
37#include <rtems/score/thread.h>
38#include <stdio.h>
39#include <stdlib.h>
40
41void a29k_ISR_Handler(unsigned32 vector);
42
43/*  _CPU_Initialize
44 *
45 *  This routine performs processor dependent initialization.
46 *
47 *  INPUT PARAMETERS:
48 *    cpu_table       - CPU table to initialize
49 *    thread_dispatch - address of disptaching routine
50 */
51
52
53void _CPU_Initialize(
54  rtems_cpu_table  *cpu_table,
55  void      (*thread_dispatch)()      /* ignored on this CPU */
56)
57{
58  unsigned int i;
59  /*
60   *  The thread_dispatch argument is the address of the entry point
61   *  for the routine called at the end of an ISR once it has been
62   *  decided a context switch is necessary.  On some compilation
63   *  systems it is difficult to call a high-level language routine
64   *  from assembly.  This allows us to trick these systems.
65   *
66   *  If you encounter this problem save the entry point in a CPU
67   *  dependent variable.
68   */
69
70  _CPU_Thread_dispatch_pointer = thread_dispatch;
71
72  /*
73   *  If there is not an easy way to initialize the FP context
74   *  during Context_Initialize, then it is usually easier to
75   *  save an "uninitialized" FP context here and copy it to
76   *  the task's during Context_Initialize.
77   */
78
79  /* FP context initialization support goes here */
80
81  _CPU_Table = *cpu_table;
82
83  for ( i = 0; i < ISR_NUMBER_OF_VECTORS; i++ )
84  {
85     _ISR_Vector_table[i] = (proc_ptr)NULL;
86  }
87}
88
89/*PAGE
90 *
91 *  _CPU_ISR_Get_level
92 */
93 
94unsigned32 _CPU_ISR_Get_level( void )
95{
96  unsigned32    cps;
97
98  /*
99   *  This routine returns the current interrupt level.
100   */
101  cps = a29k_getops();
102  if (cps & (TD|DI))
103    return 1;
104  else
105    return 0;
106}
107
108/*PAGE
109 *
110 *  _CPU_ISR_install_raw_handler
111 */
112 
113extern void intr14( void );
114extern void intr18( void );
115extern void intr19( void );
116
117/* just to link with GNU tools JRS 09/22/2000 */
118asm (".global V_SPILL, V_FILL" );
119asm (".global V_EPI_OS, V_BSD_OS" );
120
121asm (".equ    V_SPILL, 64" );
122asm (".equ    V_FILL, 65" );
123
124asm (".equ    V_BSD_OS, 66" );
125asm (".equ    V_EPI_OS, 69" );
126
127/* end of just to link with GNU tools */
128
129void _CPU_ISR_install_raw_handler(
130  unsigned32  vector,
131  proc_ptr    new_handler,
132  proc_ptr   *old_handler
133)
134{
135  /*
136   *  This is where we install the interrupt handler into the "raw" interrupt
137   *  table used by the CPU to dispatch interrupt handlers.
138   */
139   switch( vector )
140   {
141/* where is this code? JRS */
142#if 0
143      case 14:
144         _settrap( vector, intr14 );
145         break;
146      case 18:
147         _settrap( vector, intr18 );
148         break;
149      case 19:
150         _settrap( vector, intr19 );
151         break;
152#endif
153
154      default:
155         break;
156   }
157}
158
159
160/*PAGE
161 *
162 *  _CPU_ISR_install_vector
163 *
164 *  This kernel routine installs the RTEMS handler for the
165 *  specified vector.
166 *
167 *  Input parameters:
168 *    vector      - interrupt vector number
169 *    old_handler - former ISR for this vector number
170 *    new_handler - replacement ISR for this vector number
171 *
172 *  Output parameters:  NONE
173 *
174 */
175
176void _CPU_ISR_install_vector(
177  unsigned32  vector,
178  proc_ptr    new_handler,
179  proc_ptr   *old_handler
180)
181{
182   *old_handler = _ISR_Vector_table[ vector ];
183
184   /*
185    *  If the interrupt vector table is a table of pointer to isr entry
186    *  points, then we need to install the appropriate RTEMS interrupt
187    *  handler for this vector number.
188    */
189
190   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
191
192   /*
193    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
194    *  be used by the _ISR_Handler so the user gets control.
195    */
196
197    _ISR_Vector_table[ vector ] = new_handler;
198}
199
200/*PAGE
201 *
202 *  _CPU_Install_interrupt_stack
203 */
204
205void _CPU_Install_interrupt_stack( void )
206{
207}
208
209/*PAGE
210 *
211 *  _CPU_Thread_Idle_body
212 *
213 *  NOTES:
214 *
215 *  1. This is the same as the regular CPU independent algorithm.
216 *
217 *  2. If you implement this using a "halt", "idle", or "shutdown"
218 *     instruction, then don't forget to put it in an infinite loop.
219 *
220 *  3. Be warned. Some processors with onboard DMA have been known
221 *     to stop the DMA if the CPU were put in IDLE mode.  This might
222 *     also be a problem with other on-chip peripherals.  So use this
223 *     hook with caution.
224 */
225
226void _CPU_Thread_Idle_body( void )
227{
228
229  for( ; ; )
230  {
231  }
232    /* insert your "halt" instruction here */ ;
233}
234
235void a29k_fatal_error( unsigned32 error )
236{
237   printf("\n\nfatal error %d, rebooting!!!\n",error );
238   exit(error);
239}
240
241   /*
242    *  This discussion ignores a lot of the ugly details in a real
243    *  implementation such as saving enough registers/state to be
244    *  able to do something real.  Keep in mind that the goal is
245    *  to invoke a user's ISR handler which is written in C and
246    *  uses a certain set of registers.
247    *
248    *  Also note that the exact order is to a large extent flexible.
249    *  Hardware will dictate a sequence for a certain subset of
250    *  _ISR_Handler while requirements for setting
251    */
252
253  /*
254   *  At entry to "common" _ISR_Handler, the vector number must be
255   *  available.  On some CPUs the hardware puts either the vector
256   *  number or the offset into the vector table for this ISR in a
257   *  known place.  If the hardware does not give us this information,
258   *  then the assembly portion of RTEMS for this port will contain
259   *  a set of distinct interrupt entry points which somehow place
260   *  the vector number in a known place (which is safe if another
261   *  interrupt nests this one) and branches to _ISR_Handler.
262   *
263   */
264
265void a29k_ISR_Handler(unsigned32 vector)
266{
267   _ISR_Nest_level++;
268   _Thread_Dispatch_disable_level++;
269   if ( _ISR_Vector_table[ vector ] )
270      (*_ISR_Vector_table[ vector ])( vector );
271   --_Thread_Dispatch_disable_level;
272   --_ISR_Nest_level;
273
274   if ( _ISR_Nest_level )
275     return;
276
277   if ( _Thread_Dispatch_disable_level ) {
278     _ISR_Signals_to_thread_executing = FALSE;
279     return;
280   }
281
282   if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
283     _ISR_Signals_to_thread_executing = FALSE;
284     _Thread_Dispatch();
285   }
286}
Note: See TracBrowser for help on using the repository browser.