[a4d97d94] | 1 | /* |
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| 2 | * AMD 29K CPU Dependent Source |
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| 3 | * |
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| 4 | * Author: Craig Lebakken <craigl@transition.com> |
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| 5 | * |
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| 6 | * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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| 7 | * |
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| 8 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 9 | * without any express or implied warranty: |
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| 10 | * permission to use, copy, modify, and distribute this file |
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| 11 | * for any purpose is hereby granted without fee, provided that |
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| 12 | * the above copyright notice and this notice appears in all |
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| 13 | * copies, and that the name of Transition Networks not be used in |
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| 14 | * advertising or publicity pertaining to distribution of the |
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| 15 | * software without specific, written prior permission. |
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| 16 | * Transition Networks makes no representations about the suitability |
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| 17 | * of this software for any purpose. |
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| 18 | * |
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| 19 | * Derived from c/src/exec/score/cpu/no_cpu/cpu.c: |
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| 20 | * |
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| 21 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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| 22 | * On-Line Applications Research Corporation (OAR). |
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| 23 | * All rights assigned to U.S. Government, 1994. |
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| 24 | * |
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| 25 | * This material may be reproduced by or for the U.S. Government pursuant |
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| 26 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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| 27 | * notice must appear in all copies of this file and its derivatives. |
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| 28 | * |
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| 29 | * $Id$ |
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| 30 | */ |
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| 31 | #ifndef lint |
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[29d8227e] | 32 | static char _sccsid[] = "@(#)cpu.c 10/21/96 1.8\n"; |
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[a4d97d94] | 33 | #endif |
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| 34 | |
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| 35 | #include <rtems/system.h> |
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| 36 | #include <rtems/score/isr.h> |
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| 37 | #include <rtems/score/wkspace.h> |
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| 38 | #include <rtems/score/thread.h> |
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| 39 | #include <stdio.h> |
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| 40 | #include <stdlib.h> |
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| 41 | |
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| 42 | void a29k_ISR_Handler(unsigned32 vector); |
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| 43 | |
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| 44 | /* _CPU_Initialize |
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| 45 | * |
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| 46 | * This routine performs processor dependent initialization. |
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| 47 | * |
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| 48 | * INPUT PARAMETERS: |
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| 49 | * cpu_table - CPU table to initialize |
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| 50 | * thread_dispatch - address of disptaching routine |
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| 51 | */ |
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| 52 | |
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| 53 | |
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| 54 | void _CPU_Initialize( |
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| 55 | rtems_cpu_table *cpu_table, |
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| 56 | void (*thread_dispatch)() /* ignored on this CPU */ |
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| 57 | ) |
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| 58 | { |
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| 59 | unsigned int i; |
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| 60 | /* |
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| 61 | * The thread_dispatch argument is the address of the entry point |
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| 62 | * for the routine called at the end of an ISR once it has been |
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| 63 | * decided a context switch is necessary. On some compilation |
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| 64 | * systems it is difficult to call a high-level language routine |
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| 65 | * from assembly. This allows us to trick these systems. |
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| 66 | * |
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| 67 | * If you encounter this problem save the entry point in a CPU |
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| 68 | * dependent variable. |
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| 69 | */ |
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| 70 | |
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| 71 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
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| 72 | |
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| 73 | /* |
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| 74 | * If there is not an easy way to initialize the FP context |
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| 75 | * during Context_Initialize, then it is usually easier to |
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| 76 | * save an "uninitialized" FP context here and copy it to |
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| 77 | * the task's during Context_Initialize. |
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| 78 | */ |
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| 79 | |
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| 80 | /* FP context initialization support goes here */ |
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| 81 | |
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| 82 | _CPU_Table = *cpu_table; |
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| 83 | |
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| 84 | for ( i = 0; i < ISR_NUMBER_OF_VECTORS; i++ ) |
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| 85 | { |
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| 86 | _ISR_Vector_table[i] = (proc_ptr)NULL; |
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| 87 | } |
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| 88 | } |
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| 89 | |
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| 90 | /*PAGE |
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| 91 | * |
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| 92 | * _CPU_ISR_Get_level |
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| 93 | */ |
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| 94 | |
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| 95 | unsigned32 _CPU_ISR_Get_level( void ) |
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| 96 | { |
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[29d8227e] | 97 | unsigned32 cps; |
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| 98 | |
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[a4d97d94] | 99 | /* |
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| 100 | * This routine returns the current interrupt level. |
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| 101 | */ |
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[29d8227e] | 102 | cps = a29k_getops(); |
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| 103 | if (cps & (TD|DI)) |
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| 104 | return 1; |
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| 105 | else |
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| 106 | return 0; |
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[a4d97d94] | 107 | } |
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| 108 | |
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| 109 | /*PAGE |
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| 110 | * |
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| 111 | * _CPU_ISR_install_raw_handler |
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| 112 | */ |
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| 113 | |
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| 114 | extern void intr14( void ); |
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[29d8227e] | 115 | extern void intr18( void ); |
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| 116 | extern void intr19( void ); |
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[a4d97d94] | 117 | |
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| 118 | void _CPU_ISR_install_raw_handler( |
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| 119 | unsigned32 vector, |
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| 120 | proc_ptr new_handler, |
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| 121 | proc_ptr *old_handler |
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| 122 | ) |
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| 123 | { |
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| 124 | /* |
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| 125 | * This is where we install the interrupt handler into the "raw" interrupt |
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| 126 | * table used by the CPU to dispatch interrupt handlers. |
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| 127 | */ |
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| 128 | switch( vector ) |
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| 129 | { |
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| 130 | case 14: |
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| 131 | _settrap( vector, intr14 ); |
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| 132 | break; |
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[29d8227e] | 133 | case 18: |
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| 134 | _settrap( vector, intr18 ); |
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[a4d97d94] | 135 | break; |
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[29d8227e] | 136 | case 19: |
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| 137 | _settrap( vector, intr19 ); |
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[a4d97d94] | 138 | break; |
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[29d8227e] | 139 | |
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[a4d97d94] | 140 | default: |
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| 141 | break; |
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| 142 | } |
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| 143 | } |
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| 144 | |
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| 145 | |
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| 146 | /*PAGE |
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| 147 | * |
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| 148 | * _CPU_ISR_install_vector |
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| 149 | * |
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| 150 | * This kernel routine installs the RTEMS handler for the |
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| 151 | * specified vector. |
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| 152 | * |
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| 153 | * Input parameters: |
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| 154 | * vector - interrupt vector number |
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| 155 | * old_handler - former ISR for this vector number |
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| 156 | * new_handler - replacement ISR for this vector number |
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| 157 | * |
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| 158 | * Output parameters: NONE |
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| 159 | * |
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| 160 | */ |
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| 161 | |
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| 162 | void _CPU_ISR_install_vector( |
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| 163 | unsigned32 vector, |
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| 164 | proc_ptr new_handler, |
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| 165 | proc_ptr *old_handler |
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| 166 | ) |
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| 167 | { |
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| 168 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 169 | |
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| 170 | /* |
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| 171 | * If the interrupt vector table is a table of pointer to isr entry |
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| 172 | * points, then we need to install the appropriate RTEMS interrupt |
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| 173 | * handler for this vector number. |
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| 174 | */ |
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| 175 | |
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| 176 | _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); |
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| 177 | |
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| 178 | /* |
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| 179 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 180 | * be used by the _ISR_Handler so the user gets control. |
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| 181 | */ |
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| 182 | |
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| 183 | _ISR_Vector_table[ vector ] = new_handler; |
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| 184 | } |
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| 185 | |
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| 186 | /*PAGE |
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| 187 | * |
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| 188 | * _CPU_Install_interrupt_stack |
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| 189 | */ |
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| 190 | |
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| 191 | void _CPU_Install_interrupt_stack( void ) |
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| 192 | { |
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| 193 | } |
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| 194 | |
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| 195 | /*PAGE |
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| 196 | * |
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| 197 | * _CPU_Internal_threads_Idle_thread_body |
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| 198 | * |
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| 199 | * NOTES: |
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| 200 | * |
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| 201 | * 1. This is the same as the regular CPU independent algorithm. |
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| 202 | * |
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| 203 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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| 204 | * instruction, then don't forget to put it in an infinite loop. |
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| 205 | * |
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| 206 | * 3. Be warned. Some processors with onboard DMA have been known |
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| 207 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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| 208 | * also be a problem with other on-chip peripherals. So use this |
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| 209 | * hook with caution. |
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| 210 | */ |
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| 211 | |
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| 212 | void _CPU_Internal_threads_Idle_thread_body( void ) |
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| 213 | { |
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| 214 | |
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| 215 | for( ; ; ) |
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| 216 | { |
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| 217 | } |
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| 218 | /* insert your "halt" instruction here */ ; |
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| 219 | } |
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| 220 | |
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| 221 | void a29k_fatal_error( unsigned32 error ) |
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| 222 | { |
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| 223 | printf("\n\nfatal error %d, rebooting!!!\n",error ); |
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| 224 | exit(error); |
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| 225 | } |
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| 226 | |
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| 227 | /* |
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| 228 | * This discussion ignores a lot of the ugly details in a real |
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| 229 | * implementation such as saving enough registers/state to be |
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| 230 | * able to do something real. Keep in mind that the goal is |
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| 231 | * to invoke a user's ISR handler which is written in C and |
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| 232 | * uses a certain set of registers. |
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| 233 | * |
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| 234 | * Also note that the exact order is to a large extent flexible. |
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| 235 | * Hardware will dictate a sequence for a certain subset of |
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| 236 | * _ISR_Handler while requirements for setting |
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| 237 | */ |
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| 238 | |
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| 239 | /* |
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| 240 | * At entry to "common" _ISR_Handler, the vector number must be |
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| 241 | * available. On some CPUs the hardware puts either the vector |
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| 242 | * number or the offset into the vector table for this ISR in a |
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| 243 | * known place. If the hardware does not give us this information, |
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| 244 | * then the assembly portion of RTEMS for this port will contain |
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| 245 | * a set of distinct interrupt entry points which somehow place |
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| 246 | * the vector number in a known place (which is safe if another |
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| 247 | * interrupt nests this one) and branches to _ISR_Handler. |
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| 248 | * |
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| 249 | */ |
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| 250 | |
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| 251 | void a29k_ISR_Handler(unsigned32 vector) |
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| 252 | { |
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| 253 | _ISR_Nest_level++; |
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| 254 | _Thread_Dispatch_disable_level++; |
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| 255 | if ( _ISR_Vector_table[ vector ] ) |
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| 256 | (*_ISR_Vector_table[ vector ])( vector ); |
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| 257 | --_Thread_Dispatch_disable_level; |
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| 258 | --_ISR_Nest_level; |
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| 259 | if ( !_Thread_Dispatch_disable_level && !_ISR_Nest_level && |
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| 260 | (_Context_Switch_necessary || _ISR_Signals_to_thread_executing )) |
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| 261 | _Thread_Dispatch(); |
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| 262 | return; |
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| 263 | } |
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